Mr. Lokesh Subramany Profile

Lokesh Subramany

Principal Engineer at GLOBALFOUNDRIES Inc

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Author

Publications (19)

Proceedings Article | 24 March 2017 Paper

Novel methodology to optimize wafer alignment to enhance 14nm on product overlay

Pavan Samudrala, Woong Jae Chung, Lokesh Subramany, Haiyong Gao, Nyan Aung, Seung Chul Oh, Shawn Lee, Erik Delvigne, Blandine Minghetti

Proceedings Volume 10147, 101471U (2017) https://doi.org/10.1117/12.2258137

KEYWORDS: Optical alignment, Overlay metrology, Scanners, Yield improvement, Lithium, Data modeling, Roads

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Proceedings Article | 24 March 2017 Paper

Alignment solutions on FBEOL layers using ASML scanners

Pavan Samudrala, Gregory Hart, Yen-Jen Chen, Lokesh Subramany, Haiyong Gao, Nyan Aung, Woong Jae Chung, Blandine Minghetti, Rajan Mali, Seva Khikhlovskyi, Pieter Heres

Proceedings Volume 10147, 101471T (2017) https://doi.org/10.1117/12.2258128

KEYWORDS: Optical alignment, Sensors, Scanners, Aluminum, Near infrared, Laser beam diagnostics

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Proceedings Article | 21 April 2016 Paper

Analysis of wafer heating in 14nm DUV layers

Lokesh Subramany, Woong Jae Chung, Pavan Samudrala, Haiyong Gao, Nyan Aung, Juan Manuel Gomez, Blandine Minghetti, Shawn Lee

Proceedings Volume 9778, 97780U (2016) https://doi.org/10.1117/12.2218724

KEYWORDS: Semiconducting wafers, Overlay metrology, Deep ultraviolet, Scanners, Process control, Photomasks, Reticles, Metrology, Metals, Data modeling, Image enhancement

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Proceedings Article | 18 March 2016 Paper

Advanced overlay: sampling and modeling for optimized run-to-run control

Lokesh Subramany, WoongJae Chung, Pavan Samudrala, Haiyong Gao, Nyan Aung, Juan Manuel Gomez, Karsten Gutjahr, DongSuk Park, Patrick Snow, Miguel Garcia-Medina, Lipkong Yap, Onur Nihat Demirer, Bill Pierson, John Robinson

Proceedings Volume 9778, 97782K (2016) https://doi.org/10.1117/12.2218729

KEYWORDS: Semiconducting wafers, Data modeling, Overlay metrology, Metrology, Process control, Scanners, Mathematical modeling, High volume manufacturing

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In recent years overlay (OVL) control schemes have become more complicated in order to meet the ever shrinking margins of advanced technology nodes. As a result, this brings up new challenges to be addressed for effective run-to- run OVL control. This work addresses two of these challenges by new advanced analysis techniques: (1) sampling optimization for run-to-run control and (2) bias-variance tradeoff in modeling. The first challenge in a high order OVL control strategy is to optimize the number of measurements and the locations on the wafer, so that the “sample plan” of measurements provides high quality information about the OVL signature on the wafer with acceptable metrology throughput. We solve this tradeoff between accuracy and throughput by using a smart sampling scheme which utilizes various design-based and data-based metrics to increase model accuracy and reduce model uncertainty while avoiding wafer to wafer and within wafer measurement noise caused by metrology, scanner or process. This sort of sampling scheme, combined with an advanced field by field extrapolated modeling algorithm helps to maximize model stability and minimize on product overlay (OPO). Second, the use of higher order overlay models means more degrees of freedom, which enables increased capability to correct for complicated overlay signatures, but also increases sensitivity to process or metrology induced noise. This is also known as the bias-variance trade-off. A high order model that minimizes the bias between the modeled and raw overlay signature on a single wafer will also have a higher variation from wafer to wafer or lot to lot, that is unless an advanced modeling approach is used. In this paper, we characterize the bias-variance trade off to find the optimal scheme. The sampling and modeling solutions proposed in this study are validated by advanced process control (APC) simulations to estimate run-to-run performance, lot-to-lot and wafer-to- wafer model term monitoring to estimate stability and ultimately high volume manufacturing tests to monitor OPO by densely measured OVL data.

Proceedings Article | 8 March 2016 Paper

Scanner baseliner monitoring and control in high volume manufacturing

Pavan Samudrala, Woong Jae Chung, Nyan Aung, Lokesh Subramany, Haiyong Gao, Juan-Manuel Gomez

Proceedings Volume 9778, 977838 (2016) https://doi.org/10.1117/12.2218162

KEYWORDS: Overlay metrology, Scanners, Data modeling, High volume manufacturing, Process control, Manufacturing, Performance modeling, Metrology, Statistical modeling

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Proceedings Article | 8 March 2016 Paper

Comparison study of diffraction based overlay and image based overlay measurements on programmed overlay errors

Haiyong Gao, Woong Jae Chung, Nyan Aung, Lokesh Subramany, Pavan Samudrala, Juan-Manuel Gomez

Proceedings Volume 9778, 97782Q (2016) https://doi.org/10.1117/12.2218163

KEYWORDS: Overlay metrology, Metrology, Diffraction, Process control, Lithography, Semiconductor manufacturing, Error analysis, Reticles, Semiconducting wafers

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Proceedings Article | 8 March 2016 Paper

Overlay optimization for 1x node technology and beyond via rule based sparse sampling

Nyan Aung, Woong Jae Chung, Lokesh Subramany, Shehzeen Hussain, Pavan Samudrala, Haiyong Gao, Xueli Hao, Yen-Jen Chen, Juan-Manuel Gomez

Proceedings Volume 9778, 97782G (2016) https://doi.org/10.1117/12.2218161

KEYWORDS: Overlay metrology, Metrology, Process control, Statistical modeling, Semiconducting wafers, Scanners, Data centers, MATLAB, Manganese, Semiconductor manufacturing, High volume manufacturing

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Proceedings Article | 20 March 2015 Paper

Process variation challenges and resolution in the negative-tone develop double patterning for 20nm and below technology node

Sohan Mehta, Lakshmi Ganta, Vikrant Chauhan, Yixu Wu, Sunil Singh, Chia Ann, Lokesh Subramany, Craig Higgins, Burcin Erenturk, Ravi Srivastava, Paramjit Singh, Hui Peng Koh, David Cho

Proceedings Volume 9425, 94250B (2015) https://doi.org/10.1117/12.2087546

KEYWORDS: Critical dimension metrology, Binary data, Double patterning technology, Etching, Photomasks, Photoresist processing, Nanoimprint lithography, Image processing, Optical lithography, Neodymium

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Immersion based 20nm technology node and below becoming very challenging to chip designers, process and integration due to multiple patterning to integrate one design layer . Negative tone development (NTD) processes have been well accepted by industry experts for enabling technologies 20 nm and below. 193i double patterning is the technology solution for pitch down to 80 nm. This imposes tight control in critical dimension(CD) variation in double patterning where design patterns are decomposed in two different masks such as in litho-etch-litho etch (LELE). CD bimodality has been widely studied in LELE double patterning. A portion of CD tolerance budget is significantly consumed by variations in CD in double patterning.

The objective of this work is to study the process variation challenges and resolution in the Negative Tone Develop Process for 20 nm and Below Technology Node. This paper describes the effect of dose slope on CD variation in negative tone develop LELE process. This effect becomes even more challenging with standalone NTD developer process due to q-time driven CD variation. We studied impact of different stacks with combination of binary and attenuated phase shift mask and estimated dose slope contribution individually from stack and mask type. Mask 3D simulation was carried out to understand theoretical aspect. In order to meet the minimum insulator requirement for the worst case on wafer the overlay and critical dimension uniformity (CDU) budget margins have slimmed. Besides the litho process and tool control using enhanced metrology feedback, the variation control has other dependencies too. Color balancing between the two masks in LELE is helpful in countering effects such as iso-dense bias, and pattern shifting. Dummy insertion and the improved decomposition techniques [2] using multiple lower priority constraints can help to a great extent. Innovative color aware routing techniques [3] can also help with achieving more uniform density and color balanced layouts.

Proceedings Article | 19 March 2015 Paper

Signal response metrology (SRM): a new approach for lithography metrology

Stilian Pandev, Fang Fang, Young Ki Kim, Jamie Tsai, Alok Vaid, Lokesh Subramany, Dimitry Sanko, Vidya Ramanathan, Ren Zhou, Kartik Venkataraman, Ronny Haupt

Proceedings Volume 9424, 94241P (2015) https://doi.org/10.1117/12.2086056

KEYWORDS: Semiconducting wafers, Metrology, Finite element methods, Critical dimension metrology, Scanners, Single crystal X-ray diffraction, Scatterometry, Model-based design, Data modeling, Lithography

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Proceedings Article | 19 March 2015 Paper

Overlay target selection for 20-nm process on A500 LCM

Vidya Ramanathan, Lokesh Subramany, Tal Itzkovich, Karsten Gutjhar, Patrick Snow, Chanseob Cho, Lipkong Yap

Proceedings Volume 9424, 942424 (2015) https://doi.org/10.1117/12.2086016

KEYWORDS: Overlay metrology, Semiconducting wafers, Back end of line, Etching, Scatterometry, Metrology, Diffractive optical elements, Front end of line, Optical properties, Inspection

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Proceedings Article | 19 March 2015 Paper

HVM capabilities of CPE run-to-run overlay control

Lokesh Subramany, Woong Jae Chung, Karsten Gutjahr, Miguel Garcia-Medina, Christian Sparka, Lipkong Yap, Onur Demirer, Ramkumar Karur-Shanmugam, Brent Riggs, Vidya Ramanathan, John Robinson, Bill Pierson

Proceedings Volume 9424, 94241V (2015) https://doi.org/10.1117/12.2190852

KEYWORDS: Semiconducting wafers, Overlay metrology, Control systems, Optical parametric oscillators, Scanners, Process control, High volume manufacturing, Metrology, Yield improvement, Error analysis

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Proceedings Article | 14 April 2014 Paper

Run time scanner data analysis for HVM lithography process monitoring and stability control

Woong Jae Chung, Young Ki Kim, John Tristan, Jeong Soo Kim, Lokesh Subramany, Chen Li, Brent Riggs, Vidya Ramanathan, Ram Karur-Shanmugam, George Hoo, Jie Gao, Anna Golotsvan, Kevin Huang, Bill Pierson, John Robinson

Proceedings Volume 9050, 90502J (2014) https://doi.org/10.1117/12.2046330

KEYWORDS: Optical alignment, Scanners, Semiconducting wafers, Lithography, Visualization, Data analysis, Statistical analysis, Atomic force microscopy, Visual analytics, Data modeling

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Proceedings Article | 2 April 2014 Paper

Lithography focus/exposure control and corrections to improve CDU at post etch step

Young Ki Kim, Mark Yelverton, John Tristan, Joungchel Lee, Karsten Gutjahr, Ching-Hsiang Hsu, Hong Wei, Lester Wang, Chen Li, Lokesh Subramany, Woong Jae Chung, Jeong Soo Kim, Vidya Ramanathan, LipKong Yap, Jie Gao, Ram Karur-Shanmugam, Anna Golotsvan, Pedro Herrera, Kevin Huang, Bill Pierson

Proceedings Volume 9050, 90501Y (2014) https://doi.org/10.1117/12.2045433

KEYWORDS: Semiconducting wafers, Etching, Lithography, Finite element methods, Scatterometry, Critical dimension metrology, Factory automation, Scanners, High volume manufacturing, Scatter measurement

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Proceedings Article | 2 April 2014 Paper

20nm MOL overlay case study

Lokesh Subramany, Michael Hsieh, Chen Li, Hui Peng Koh, David Cho, Anna Golotsvan, Vidya Ramanathan, Ramkumar Karur Shanmugam, Lipkong Yap

Proceedings Volume 9050, 90502Q (2014) https://doi.org/10.1117/12.2046598

KEYWORDS: Overlay metrology, Semiconducting wafers, Chemical mechanical planarization, Optical alignment, Metrology, Image quality, Optical filters, Image processing, Reticles, Scanners

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Proceedings Article | 2 April 2014 Paper

Integrated production overlay field-by-field control for leading edge technology nodes

Woong Jae Chung, John Tristan, Karsten Gutjahr, Lokesh Subramany, Chen Li, Yulei Sun, Mark Yelverton, Young Ki Kim, Jeong Soo Kim, Chin-Chou Kevin Huang, William Pierson, Ramkumar Karur-Shanmugam, Brent Riggs, Sven Jug, John Robinson, Lipkong Yap, Vidya Ramanathan

Proceedings Volume 9050, 90501P (2014) https://doi.org/10.1117/12.2046076

KEYWORDS: Scanners, Semiconducting wafers, Overlay metrology, Control systems, Statistical modeling, Error analysis, Data modeling, Optical lithography, Process control, Atomic force microscopy

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Proceedings Article | 2 April 2014 Paper

Evaluation of lens heating effect in high transmission NTD processes at the 20nm technology node

Bumhwan Jeon, Sam Lee, Lokesh Subramany, Chen Li, Shyam Pal, Sheldon Meyers, Sohan Mehta, Yayi Wei, David Cho

Proceedings Volume 9050, 90501U (2014) https://doi.org/10.1117/12.2034206

KEYWORDS: Semiconducting wafers, Reticles, Calibration, Photomasks, Critical dimension metrology, Source mask optimization, Computational modeling, Optical lithography, Wavefronts, Overlay metrology

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Proceedings Article | 18 April 2013 Paper

High order wafer alignment for 20nm node logic process

Bumhwan Jeon, Shyam Pal, Sohan Mehta, Subramany Lokesh, Yun Tao Jiang, Chen Li, Mark Yelverton, Yayi Wei

Proceedings Volume 8681, 868110 (2013) https://doi.org/10.1117/12.2010709

KEYWORDS: Semiconducting wafers, Optical alignment, Distortion, Overlay metrology, Annealing, Transistors, Logic, Laser processing, Lithography, Semiconductor manufacturing

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Proceedings Article | 10 April 2013 Paper

Implementation of hybrid metrology at HVM fab for 20nm and beyond

Alok Vaid, Lokesh Subramany, Givantha Iddawela, Carl Ford, John Allgair, Gaurav Agrawal, John Taylor, Carsten Hartig, Byung Cheol (Charles) Kang, Cornel Bozdog, Matthew Sendelbach, Paul Isbester, Limor Issascharoff

Proceedings Volume 8681, 868103 (2013) https://doi.org/10.1117/12.2012339

KEYWORDS: Metrology, Semiconducting wafers, Critical dimension metrology, Transmission electron microscopy, Etching, Process control, Reactive ion etching, Data modeling, High volume manufacturing

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Proceedings Article | 29 March 2013 Paper

Investigation of trench and contact hole shrink mechanism in the negative tone develop process

Sohan Singh Mehta, Craig Higgins, Vikrant Chauhan, Shyam Pal, Hui Peng Koh, Jean Raymond Fakhoury, Shaowen Gao, Lokesh Subramany, Salman Iqbal, Bumhwan Jeon, Pedro Morrison, Chris Karanikas, Yayi Wei, David Cho

Proceedings Volume 8682, 86820O (2013) https://doi.org/10.1117/12.2012331

KEYWORDS: Diffusion, Critical dimension metrology, Polymers, Photoresist processing, Image processing, Manufacturing, Lithography, Optical lithography, Data modeling, Modulation

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Showing 5 of 19 publications

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