Time-of-flight secondary-ion mass spectrometry (TOF-SIMS) imaging is demonstrated as a sensitive qualitative method
for characterizing surface acid concentrations and accompanying chemical changes at resist surfaces. We show its utility
in analyzing the 'chemical flare' phenomenon associated with some chemically amplified photoresists. Two commercial
193 nm photoresists were studied: 'photoresist A' displays lithographic defects linked to chemical flare at die edges;
'photoresist B' does not. TOF-SIMS imaging of the surface of 'photoresist A' following exposure and post-exposure
bake (PEB) reveals that die edge defects are well correlated with pronounced emanation of surface acid concentrations
from, and blocking group depletion beyond, the die edge. Both photoresists also exhibit longer-range surface
acidification that is not well correlated with lithographic effects. A plurality of evidence leads us to infer that photoacid
migration from exposed to unexposed regions underlies the lithographic defects observed in 'photoresist A.'
Patterning of dense gratings with sub-wavelength pitches presents a challenge that can be addressed using Resolution Enhancement Techniques (RETs) such as dipole illumination, with the dipole axis perpendicular to the dense line orientation. However, this approach leads to pitch and orientation limitations that must be accommodated in layout practices and design rules. In this work we evaluate the impact that dipole illumination has on the process window of isolated lines and loose pitch lines parallel and orthogonal to the dipole axis, and demonstrate the use of OPC and design restrictions to minimize this impact. Semi-dense and isolated features need to be treated as a function of their orientation with respect to the dipole. Specifically, isolated features oriented along the axis of the dipole have larger process margins than the same feature oriented perpendicular to this axis. We systematically explore the process margins for various CDs, pitches and orientations, and compare the results with simulations. We demonstrate that the dipole illumination restricts the ranges of sizes, pitches and orientations that can be printed with sufficient process margin. Knowledge of these restrictions and comparing them with simulation enables us to evaluate the suitability of simulations as a predictor for design rules to restrict layout. The results enable us to propose design rules that would enable single-mask solutions for layers using dipole illumination.
Early insertion of ArF nm lithography will occur at the 130 nm node in 2001. Process development for the 100 nm node will also occur this year. Both aggressive gate length reductions and minimum pitch design rules below 250 nm present immediate challenges for the new ArF technology. Gate line widths with approach one half of the wavelength of the exposure system. Contact holes and dark field mask trench structures for 100 nm node will require use of high NA ArF scanners as well as advanced illumination conditions. Development of processes utilizing OPC and PSM as well as advanced illumination conditions are critical to achieving adequate resolution, process latitude, and CD control. With the introduction of very low k1 processes the pattern collapse problem that was anticipated for NGL lithography is upon us today. Another result of sub-wavelength patterning and low contrast images is that the CD variation in the photomask gives rise to a larger than expected printed CD changes: the so-called MEEF (Mask Error Enhancement Factor). The MEEF can be defined as the slope of the litho process linearity curve. This paper will address pattern collapse and CD control issues for bright and dark field images using a full field ArF scanner. We will demonstrate that the resist choice, dark field and bright field printing, feature size and pitch, process conditions, as well as illumination conditions influence the process non- linearity and MEEF. We will compare this with resolution capability and MEEF of modern KrF resist and attempt to quantify the maturity of ArF resist technology. The CD range of 90 - 140 nm is studied using binary masks, as well as alternating and attenuated PSM masks with ArF exposure. We will examine the possibility of optical proximity corrections for dark field structures with low and high MEEF.
Early insertion of ArF nm lithography will occur at the 130 nm node in 2001. Process development for the 100nm node will also occur this year. Both aggressive gate length reductions and minimum pitch design rules below 250nm present immediate challenges for the new ArF technology. Gate line widths will approach one half of the wavelength of the exposure system.
As lithographic technology nodes advance beyond the 193 nm generation, the optical absorption of organic materials will require the use of thin layer imaging (TLI) techniques. Of the techniques under consideration, the use of ultra-thin resist (UTR) over a hardmask is the most desirable because of its simplicity and close similarity to standard single layer resist processes. Prior work has demonstrated that the UTR process is capable of pattern transfer to poly silicon device layers with as little as 1000 Angstrom of resist on flat wafers using 248 nm lithography. This was achieved with defect levels comparable to a conventional 5000 Angstrom resist process. In this work, we demonstrate 'proof of concept' by integrating the UTR process into the transistor gate module of a production device using 248 nm lithography. In doing so we focus on three key areas for manufacturability: inherent defectivity of UTR films, sensitivity of thin resist to topography, and quality of pattern transfer. We find that pinhole defects are of little concern in the UTR process after SEM review of defects on un-patterned UTR films. We show that the UTR process is sensitive to wafer topography, since it does not provide a completely planar surface over the underlying device features. Finally, we demonstrate that the UTR process is capable of reliable pattern transfer on a production device with defect levels comparable to the thicker baseline single layer resist process.
In this paper, we discuss some of the problems encountered when implementing 2-mask strong phase shifter designs for the poly gate level in logic designs. Experimental results are presented showing pattern fidelity for different reticle designs. Simulations are presented indicating the improvement in pattern fidelity that can be expected from using OPC. PSM assignment and model-based OPC correction are performed by the Calibre-OPC tool from Mentor Graphics. In conclusion we show that while fairly simple design can be used to achieve 250nm design rules, in order to achieve both pattern fidelity as well as small feature size it is necessary to use OPC to correct for pattern distortion for design rules of 180nm and below.
Resolution, R, in optical lithography is often described by the Rayleigh equation: R equals k1(lambda) /NA. Since the 0.25 um generation there has been a trend of aggressive gate length reduction for high performance devices. Leading edge logic technologies require gate CDs equal to ½to 2/3 the wavelength of the exposure system. Even with high NA steppers and scanners low k1 patterning is a requirement. Development of processes utilizing OPC and PSM technology is critical to achieving adequate process latitude and CD control. As k1 factor falls below 0.5 the image quality and contrast degrades substantially. One result of low contrast images is that the CD variation in the photomask gives rise to larger than expected printed CD changes: the so-called MEEF. The MEEF can be simply defined as the ratio of the change of the resist feature width to the change in the mask feature width, assuming constant process and illumination conditions. For a 4x mask the MEEF can be calculated.
In this paper we discuss some of the problems and solutions discovered when implementing 2-mask strong phase shifter designs for the poly gate level in logic designs. Experimental results are presented showing pattern fidelity for different reticle designs. Simulations are presented indicating the improvement in pattern fidelity that can be expected from using OPC. Simulations, PSM assignment and model-based OPC correction are performed by the Calibre WORKbench, Calibre DRC, Calibre PSMgate and Calibre OPCpro tools from Mentor Graphics. In conclusion, we show that while fairly simple designs can be used to achieve 250 nm design rules (approximately 150 nm gates), in order to achieve both pattern fidelity as well as small feature size it is necessary to use 3-layer/phase-aware model-based OPC to correct for pattern distortion for design rules of 180 nm and below (approximately 100 nm phase-shifted gates).
This study evaluates the effect of dyes, including photosensitive dyes, on resist performance such as: swing curve reduction, resist dissolution rate, resolution, dose and focus latitude, scumming, etc. The paper demonstrates good correlation between modeling of the dyed resist performance and experimental results.
The cost of expendable chemicals in the resist process is increasing and with this the economic impetus to conserve usage. The volume of liquid resist dispensed (shot size) determines the consumption rate and disposal volumes of liquid resist. The choice of resist solvent can influence the shot volume. Three formulation factors influence the shot size: (1) the surface tension of the resist and the interfacial energy of the coating surface, (2) the viscosity of the resist formulation, and (3) the evaporation rate of the solvent. The suitable resist formulation and subsequent solvent choice should be of the lowest surface tension and lowest viscosity and be balanced by an evaporation rate which allows a minimum shot volume to be spread on the surface without significant solvent loss. Of all the solvents examined, ethyl 3-ethoxy propionate (EEP) gave the lowest shot size relative to the old resist solvent standard of 2- ethoxy ethyl acetate (ECA).
The combination of dyed photoresist and top antireflection (TAR) coatings was applied to I- line and deep-UV lithography on polysilicon. Optimization of the resist layer's absorption and application of the TAR process significantly improves CD control of submicron gate level lithography.
The use of i-line lithography for the 16 to 64 Mbit DRAM device generations calls for increased performance of i-line resists. This paper reports on investigations on novel sensitizers for advanced i-line lithography, starting out with a discussion of general design criteria, then discussing methodology and results of a screening phase, and examining in greater detail a small number of selected candidates for which resolution, exposure latitude, and depth-of-focus data were obtained. Finally, a new advanced resist for i-line lithography, AZR 7500, is presented, and its performance is evaluated in terms of the above criteria as well as thermal flow resistance.
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