In this paper, we develop a sufficient methodology of machine learning based pattern classification. This sufficient methodology can deal with patterns with mirror symmetry and rotation symmetry. These are needed to classify curvilinear (CL) layouts. This methodology can perform pattern classification on complicated layouts, including both Manhattan and curvilinear shapes. It is especially useful for pattern classification in curvilinear layouts and can be applied to CL Optical Process Correction verification (CL OPCV), CL Mask Process Correction verification (CL MPCV), CL Mask Rule Checking (CL MRC), and beyond.
In this paper, we present our innovative work of using Siemens EDA Calibre® Machine Learning (ML) assisted Optical and Process Correction (OPC) verification tool to effectively capture all kinds of hotspots using one single constraint across the whole layout for each failing mechanism, for example one constraint for bridging failing mechanism, one constraint for pinching failing mechanism, etc. The pattern differentiation is accomplished by ML classifier. The output data volume is controlled by using classification limiting function instead of tuned constraints. This work significantly improves the effectiveness of capturing and not missing real hotspots yet simplifies the OPC verification recipe setup and engineering workload. The unique hotspots count on full chip using this new strategy can be at thousand level. This makes the Machine Learning assisted hotspot capture new strategy practical to prepare hotspot monitoring points for wafer verification, for example SEM inspection.
Photon absorption statistics combined with a simple model of resist chemistry triggered by each absorbed photon leads to a family of stochastic models with a Gaussian Random Field deprotection. Two important aspects of such models are discussed. First, the generalizations to stochastic reaction-diffusion models, accounting for the effects of depletion, and to models accounting for both exposure-resist stochastic and other process parameter variations, are presented. Second, several options for the stochastic metrics of EUVL processes, both meaningful and useful for lithographers and fast enough to be applicable to the full chip OPC and verification, are described, and some details of their implementations for the full-chip OPC verification and the results of tests are presented. The relation of one of the introduced stochastic metrics to the stochastic-caused variability of the electrical conductance of vertical interconnects (vias) is explained.
In this paper we present a powerful virtual metrology system to aid in-fab product lot level dispositioning and yield learning. CD and overlay measurement data of different layers are modeled across the wafers and mapped to dense dose, focus, and overlay grids. These are input processing conditions for design-specific computational lithography to predict on full-wafer, full-chip inter-layer overlap area and critical edge-to-edge distances, which are thereafter used to predict electrical failure. The system is composed of an off-line inter-layer hotspot database and an on-line real time dispositioning module. It supports complex multi-patterning stacks with or without self-aligned processes. Example runs have been conducted for 14 nm node metal and via layers, using both FEM-like and typical nominal production wafer data, and the results are as expected from lithographical point of view. Comparing with traditional wafer dispositioning based on static overlay spec and CD spec, our system outputs wafer map stacked with failed dies locations, worst case hotspots contours, root cause analysis, list of worst hotspots and worst dies for inspection, and help litho engineer make an educated decision on wafer dispositioning. This will help fab optimize CD – Overlay process window, improve yield ramp, reduce wafer rework rate, and hence reduce cost, and shorten turn-around-time. The system’s computation is fast and inline real time wafer dispositioning aided by computational lithography is made possible by the system.
A litho hotspot repair hints requires the specifications of how layout edges should be modified. Identifying how layout
edges not directly touching the hotspot region is challenging to encode in a rule set. We propose an approach using
models called Partition Response Surface Models (pRSM) to estimate the contours changes due to design layout
modifications. In this paper we present details of litho hotspot repair hint engine which uses the pRSM models to
compute the shape changes amount to resolve a litho hotspot and which can accept constraints from both design
considerations or design rule considerations.
Computing repair hints for litho hotspots is made more effective with a model of how Process Window contour bands
changes as a function of design layout changes. We have developed a modeling methodology called pRSM (Partition
Response Surface Model). In our approach, we create a family of models along with error bound estimate models. We
first classify design layout configurations into a small number of partition categories and then build a RSM model and
error bound model for each partition category. In this paper we describe our pRSM methodology and present results
illustrating the advantages of our methodology over that of traditional RSM approaches.
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