The intention of this study is to develop an immersion lithography process using advanced track solutions to achieve
world class critical dimension (CD) and defectivity performance in a state of the art manufacturing facility. This study
looks at three important topics for immersion lithography: defectivity, CD control, and wafer backside contamination.
The topic of defectivity is addressed through optimization of coat, develop, and rinse processes as well as
implementation of soak steps and bevel cleaning as part of a comprehensive defect solution. Develop and rinse
processing techniques are especially important in the effort to achieve a zero defect solution. Improved CD control is
achieved using a biased hot plate (BHP) equipped with an electrostatic chuck. This electrostatic chuck BHP (eBHP) is
not only able to operate at a very uniform temperature, but it also allows the user to bias the post exposure bake (PEB)
temperature profile to compensate for systematic within-wafer (WiW) CD non-uniformities. Optimized CD results, pre
and post etch, are presented for production wafers. Wafer backside particles can cause focus spots on an individual
wafer or migrate to the exposure tool's wafer stage and cause problems for a multitude of wafers. A basic evaluation of
the cleaning efficiency of a backside scrubber unit located on the track was performed as a precursor to a future study
examining the impact of wafer backside condition on scanner focus errors as well as defectivity in an immersion
scanner.
This paper describes the qualification work performed on a state-of-the-art immersion cluster and shows results for an
immersion process for the 45nm node. These results demonstrate full compliance with all lithographic parameters,
including CD control and defectivity. Qualification was performed on an RF3iTM wafer track from Sokudo Co., Ltd. and
a 1.2NA immersion scanner. A three-layer material stack was engineered using 820Å BARC / 1800Å ArF photoresist
covered by 900Å immersion top-coat.
After verification of tool and process cleanliness and testing the robustness of the material stack for use in the immersion
scanner, resulting photo cell monitor (PCM) defect density on a 65nm memory device was evaluated.
Critical dimension was verified using both CD-SEM and optical CD metrology. Results on a 45nm L/S pattern showed
0.55nm WIW 3sigma CD uniformity using optical CD metrology. Lot to lot CD control was tested for being below
1.5nm 3sigma. As special Soak-units were used prior to post exposure bake (PEB), the influence of post exposure delay
(PED) on the CD performance was studied and quantified.
All immersion-related modules were optimized and qualified on both 65nm products and 45nm prototypes. Additionally,
comparison data for immersion and dry lithography will be presented.
In immersion lithography process, film stacking architecture will be necessary due to film peeling. However, the
architecture will restrict lithographic area within a wafer due to top side EBR accuracy
In this paper, we report an effective film stacking architecture that also allows maximum lithographic area. This study
used a new bevel rinse system on RF3 for all materials to make suitable film stacking on the top side bevel. This
evaluation showed that the new bevel rinse system allows the maximum lithographic area and a clean wafer edge.
Patterning defects were improved with suitable film stacking.
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