Integrated technologies represent a key enabling capability for future compact and portable atomic physics systems, including optical clocks and other sensors. In this talk, I will discuss our recent demonstration of high-fidelity detection of the state of a trapped Sr+ ion with a single-photon avalanche detector (SPAD) integrated into a microfabricated surface-electrode trap. Using an adaptive technique, we achieve ion state detection in 450 us with 99.92(1)% average fidelity. I will also discuss ongoing efforts to combine integrated detectors with integrated photonics to enable ion traps that completely eliminate the need for free-space optics for light delivery and collection.
Arrays of Geiger-mode avalanche photodiodes (GmAPDs) are fabricated on a new type of engineered substrates with an epitaxial layer grown on silicon-on-insulator (SOI) wafers. The SOI-based structure facilitates rapid die-level bump bonding of the GmAPD array to a CMOS readout integrated circuit (ROIC) followed by substrate removal to make a backilluminated image sensor. To fabricate the engineered substrate, a commercial substrate with a 70-nm-thick SOI layer is implanted with BF2 ions to create a p+-doped passivation layer on the light illumination surface. Subsequently, a lightly p-doped silicon layer on which the GmAPD will be fabricated is grown using a homoepitaxy process. This approach allows for the use of chip-level hybridization to CMOS, avoiding the high cost and demanding wafer flatness and smoothness requirements of wafer-scale 3D integration processes. The new process yields cleaner wafers and allows for tighter control of detector layer thickness compared to the previous process. GmAPDs fabricated on 5-μm-thick epitaxial silicon have over 70% photon detection efficiency (PDE) when 532 nm light is focused into the center 3 μm of the device with an oxide layer that remains after substrate removal. With an anti-reflective coating, the PDE can be improved.
We have developed 2048x32 arrays of silicon Geiger-mode avalanche photodiodes (GmAPDs) for a terrain mapping lidar to be used in planetary exploration missions. These devices support single photon detection with sub-ns timing. A key performance-limiting issue with arrays is optical crosstalk, in which hot-carrier light emission produced by an avalanche triggers spurious detection events in nearby pixels. To address this challenge, we have demonstrated a deep trench isolation process. This paper will report measurements of crosstalk between pixels in silicon GmAPD arrays, measurements both before and after the arrays are hybridized to a readout integrated circuit. Initial wafer probe measurements before hybridization show order-of-magnitude crosstalk reduction in a pair of test GmAPDs separated by 25 µm. These measurements use a novel technique based on analysis of the statistics of the time difference between the first detection events during a bias pulse. The results of our measurements are consistent with simulations of optical crosstalk modeled using optical ray tracing software.
KEYWORDS: Charge-coupled devices, Semiconducting wafers, Germanium, Back end of line, Silicon, Atomic layer deposition, Sensors, Reticles, Hard x-rays, Back illuminated sensors
A germanium charge-coupled device (CCD) offers all of the advantages of silicon CCDs – notably excellent uniformity, high energy resolution, and noiseless on-chip charge summation – but covers an even broader spectral range, extending into the hard X-ray band. MIT Lincoln Laboratory has been developing germanium CCDs for applications in astrophysics, with the goal of realizing megapixel-class arrays with read noise less than a few electrons, sensitivity to both soft and hard X-rays, and high energy resolution. We recently realized our first small pixel arrays and have since been working to increase both the format and performance of these devices. In this article, we discuss performance improvements, identification of yield-limiting process steps in fabrication of frontside-illuminated devices, fabrication and analysis of our first backside-illuminated detectors, and design of prototypes which includes a 512 × 512 pixel frame-transfer CCD with 24 µm pixel pitch.
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