Dr. Michael J. May Profile

Dr. Michael J. May

at CEA-LETI

SPIE Involvement:

Author

Publications (13)

Proceedings Article | 9 April 2024 Presentation + Paper

Characterization and mitigation of local wafer deformations introduced by direct wafer-to-wafer bonding

Richard van Haren, Suwen Li, Mart Baars, Blandine Minghetti, Leon van Dijk, Ivanie Mendes, Karine Abadie, Marie-Line Pourteau, Gaëlle Mauguen, Michael May, Viorel Balan, Frank Fournel, Laurent Pain, Thomas Plach, Gernot Probst, Markus Wimplinger

Proceedings Volume 12956, 1295606 (2024) https://doi.org/10.1117/12.3010477

KEYWORDS: Wafer bonding, Semiconducting wafers, Distortion, Scanners, Silicon, Optical alignment, Deformation, Adhesion, Etching, Metrology

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A new application in the semiconductor industry that received quite some traction the past few years is bringing the transistor power delivery network to the backside of the wafer. The big gain of this change is that it frees up real estate on the frontside of the wafer, enabling a further increase of the transistor density. This so-called Back-Side Power Delivery Network (BS-PDN) application is quite challenging since it requires a direct wafer-to-wafer bonding process module. To get access to the transistor from the backside, a device wafer needs to be flipped and bonded to a carrier wafer followed by an annealing step. After these processing steps, the original substrate of the device wafer is removed by grinding and etch steps. This will enable access to the transistors from the backside of the wafer. The wafer processing continues by conventional layer deposition, lithography and etch steps, this time on the flipped wafer. Unfortunately, the bonding process module that includes the actual direct wafer-to-wafer bonding step itself, will also introduce a distortion in the device layer that has been transferred to the carrier wafer. Since the on-product overlay requirement for the first exposed layer on the backside to one of the front-side layers is tight (<10-nm today and <<5-nm in the foreseeable future), a deep understanding of the origin of the distortion fingerprint after bonding is required. In our previous work, we presented a method to isolate the distortion fingerprint due to bonding from the remaining other overlay contributors. The fingerprint we observed after linear corrections had a typical magnitude ranging from 50 to 80-nm. A clear 4-fold symmetry was observed that could be attributed to the crystal orientation of the (100) silicon substrate. We demonstrated that the scanner wafer alignment model is very capable of correcting the global 4-fold wafer distortion fingerprint. Residual levels of less than ~15-nm were shown. These residuals could be further reduced by applying a correction per exposure (CPE) recipe. We showed that performance levels of less than ~6-nm (99.7%) and ~10-nm (max) could be achieved after a 33-parameter per exposure field self-correction. The resulting wafer plots nicely revealed how to improve the overlay performance further. An increased level of residuals was found in the wafer center and at the wafer edge. In the current paper, we build upon our previous work and continue the investigation on the remaining overlay contributors that were identified previously. This time, the focus will be on the local wafer deformations that are visible after the direct wafer-to-wafer bonding step. By local we mean the distortions that manifest themselves over a very short spatial range. These local distortions cannot easily be corrected by the scanner and are typically present close to the wafer center and the wafer edge. We know that the local wafer deformation close to the wafer center is caused by the bonding pin that initiates the bond wave. To characterize the center distortion signature, we varied many experimental parameters to see the impact. We will show the impact of the die layout, the rotation of the top wafer by a 45-degrees, wafer surface properties, and substrate choice of the carrier wafer. The latter is interesting, we evaluated both (100) and (111) carrier wafers. Although the prime focus will be to improve the overlay performance on the center of the wafer, we monitor the impact of the experimental settings on the wafer edge and remaining part of the wafer as well. We present a path forward to mitigate the local distortions such that they will not be blocking for high volume production.

SPIE Journal Paper | 12 June 2023

Electron beam direct write lithography: the versatile ally of optical lithography

Fabien Laulagnet, Jacques-Alexandre Dallery, Laurent Pain, Michael May, Béatrice Hémard, Franck Garlet, Isabelle Servin, Chiara Sabbione

JM3, Vol. 22, Issue 04, 041404, (June 2023) https://doi.org/10.1117/12.10.1117/1.JMM.22.4.041404

KEYWORDS: Electron beam direct write lithography, Lithography, Semiconducting wafers, Electron beam lithography, Optical lithography, Optical alignment, Photoresist processing, Design and modelling, Overlay metrology, Silicon

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Proceedings Article | 1 May 2023 Presentation + Paper

E-beam direct write lithography: the versatile ally of optical lithography

Fabien Laulagnet, Jacques-Alexandre Dallery, Laurent Pain, Michael May, Beatrice Hémard, Franck Garlet, Isabelle Servin, Chiara Sabbione

Proceedings Volume 12497, 1249706 (2023) https://doi.org/10.1117/12.2658273

KEYWORDS: Electron beam direct write lithography, Lithography, Semiconducting wafers, Electron beam lithography, Optical alignment, Overlay metrology, Optical lithography, Design and modelling, Photoresist processing, Deep ultraviolet

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Proceedings Article | 27 April 2023 Poster + Paper

Enabling layer transfer and back-side power delivery network applications by wafer bonding and scanner correction optimizations

Richard van Haren, Suwen Li, Blandine Minghetti, Leon van Dijk, Klaas Brantjes, Frank Fournel, Gaëlle Mauguen, Ivanie Mendes, Céline Lapeyre, Marie-Line Pourteau, Michael May, Laurent Pain, Karine Abadie, Thomas Plach, Markus Wimplinger

Proceedings Volume 12496, 124962C (2023) https://doi.org/10.1117/12.2657422

KEYWORDS: Wafer bonding, Semiconducting wafers, Scanners, Silicon, Distortion, Optical alignment, Transistors, Oxides, Crystals, Etching

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Apart from the ever-continuing lateral scaling in the xy-plane to increase the transistor density, additional new concepts find their way to the semiconductor industry too. These concepts are based on making more use of the third dimension. One relatively simple idea would be to create a second layer of transistors to double the transistor density. However, the material requirements are high and the quality of the layer deposition by conventional Chemical Vapor Deposition (CVD) techniques is insufficient. Another application to free up real estate, enabling a smaller cell size and hence an increased transistor density, is to power-up the transistors from the backside. The power rails for logic devices are historically defined in the first Metal layer and consume quite some space. Bringing the power rails to the backside will free up space. However, access to the transistor layer from the backside of the wafer is far from trivial due to the presence of a 775-μm thick silicon substrate. The answer to the challenges mentioned above is wafer-to-wafer direct bonding. Although this technique is not new and already widely used in the semiconductor industry to manufacture CMOS Image Sensors (CIS), it currently finds its way to the high-end logic markets. In case of layer transfer, a crystalline silicon layer is created by bonding a Silicon-On- Insulator (SOI) wafer to the already existing device wafer. After the bonding step, the substrate of the SOI wafer will be removed leaving the crystalline silicon layer behind. Access to the transistor layer from the wafer backside can be enabled by wafer-to-wafer bonding as well. To this end, a completed device wafer will be bonded to an (un-patterned) carrier wafer. The substrate of the original device wafer will be removed, enabling access from the backside. Wafer-towafer bonding applications can only be enabled in case the induced wafer deformations are low or when they can easily be corrected during the subsequent exposures on the scanner. At CEA-Leti, a dedicated test vehicle process flow has been developed to characterize the wafer bonding-induced distortion fingerprints for both the layer transfer and the backside power delivery network applications. The wafer process flow has been simplified without losing the industry relevant on-product overlay challenges. Wafers have been created to enable an extremely dense characterization of the wafer bonding induced fingerprint. The methodology we applied enables us to isolate the wafer bonding induced distortion fingerprint, something that is difficult to do in a production environment. The Back-Side Power Delivery Network (BS-PDN) application is the most challenging one. The initial raw measured wafer distortion fingerprints are around 60 to 80-nm. These numbers can already be easily brought down by scanner corrections to ~15-nm (mean+3σ) without too much effort. However, these numbers are too large for the 2-nm technology node and beyond, and further improvement is required. The goal of this paper is to present the path forward to bring the bonding induced wafer distortion levels to 10-nm and below. We show the capability of the latest and greatest EVG bonding tool hardware and recipe settings available at the time of running the experiments in combination with the correction capability an ASML 0.33NA scanner.

Proceedings Article | 13 June 2022 Poster

Intra track backside cleaning optimization to reduce the focus spot in Immersion lithography cluster

Nathalie Frolet, Emma Porcheron, Karine Jullian, Michael May, Yuji Tanaka, Masahiko Harumoto, Raluca Tiron

Proceedings Volume PC12055, PC120550M (2022) https://doi.org/10.1117/12.2614242

KEYWORDS: Immersion lithography, Semiconducting wafers, Scanners, Plasma etching, Contamination, Scanning electron microscopy, Polymers, Polishing, Plasma, Inspection

Proceedings Article | 26 May 2022 Poster + Paper

Pattern customization on 193 immersion lithography by negative tone development process and multiple exposures

Ivanie Mendes, Michael May, Jérôme Rêche, Raluca Tiron, Aurélien Sarrazin, Olivier Dubreuil

Proceedings Volume 12051, 120510Q (2022) https://doi.org/10.1117/12.2614018

KEYWORDS: Reticles, Lithography, Semiconducting wafers, Scanners, Silicon, Overlay metrology, Scanning electron microscopy, Process control, Image processing, Photomasks, Immersion lithography

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Proceedings Article | 25 May 2022 Poster + Paper

Continuous improvement of defectivity rate and CD uniformity in immersion lithography via track co-optimization method

Jorge Nacenta Mendivil, Nathalie Frolet, Karine Jullian, Michael May, Yuji Tanaka, Alexis Royer, Masahiko Harumoto, Raluca Tiron

Proceedings Volume 12055, 120550U (2022) https://doi.org/10.1117/12.2614237

KEYWORDS: Semiconducting wafers, System on a chip, Scanning electron microscopy, Critical dimension metrology, Inspection

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Proceedings Article | 20 March 2020 Paper

Stitched overlay evaluation and improvement for large field applications

Michael May, Blandine Minghetti, Jérome Dépré, Yoann Blancquaert, Pui Lam, Céline Lapeyre, Joungchel Lee

Proceedings Volume 11325, 113251L (2020) https://doi.org/10.1117/12.2552012

KEYWORDS: Overlay metrology, Metrology, Scanners, Critical dimension metrology

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Reducing the overlay error between stacked layers is key to enabling higher pattern density and thus moving towards high performance and more cost effective devices. However, as for specific applications like macrochips with photonic interconnects and high-resolution image sensor flat panels with advance polarizers, customers require product field sizes that are larger than the maximum field size available on scanners. Those large fields are obtained by stitching together multiple standard fields. The overlay performances between two adjacent dies are as aggressive as what is usually required between two stacked layers. For this application, the well-established polynomial overlay model is not suitable as the displacement is measured relatively and the metrology sampling in the field is such that some high order nonlinear (K) terms cannot be modeled independently. Furthermore, a perfect grid is needed in mix and match production. The intrafield correction capability of the exposure tool is not the same for each process steps. For example, no intrinsic K13 can be printed for a mix and match process flow that includes an Extreme Ultra-Violet (EUV) litho step. In addition, some KrF scanners with fewer lens manipulators cannot correct for K9. Measuring the stitching and correcting it at the first layer will prevent printing K terms that are not correctable later in the process. In this paper, the need to characterize and control single-layer overlay among different pattern placement mechanisms intrinsic to the scanner was studied: optical aberrations, field-to-field position, mask placement and registration. An ASML set-up BP-XY-V3 reticle was used to generate a large experimental dataset to validate stitching models supported by Overlay Optimizer (OVO). Overlay measurements were done Resist-in-Resist using new YieldStar (YS) interlaced stitching Diffraction Based Overlay (μDBO) targets that were designed and validated. This paper will present on product metrology results of a scatterometry-based platform showing production results with focus not only on precision and on accuracy, but also assessing target performance and target-to-target delta without process influence. A high order stitching model was developed and verified on a Multi-Product Reticle for a large device application. Trench width control at the field intersection was studied then optimized with proximity correction to ensure a perfect field-to-field junction.

Proceedings Article | 19 September 2018 Paper

Application of rules-based corrections for wafer scale nanoimprint processes and evaluation of predictive models

H. Teyssedre, P. Quemere, J. Chartoire, F. Delachat, F. Boudaa, L. Perraud, M. May

Proceedings Volume 10775, 107750A (2018) https://doi.org/10.1117/12.2326106

KEYWORDS: Semiconducting wafers, Critical dimension metrology, Nanoimprint lithography, Calibration, Manufacturing, Silicon, Lithography, Coating, Data modeling, Scanning electron microscopy

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Proceedings Article | 20 March 2018 Presentation + Paper

Dependencies of bias tables to pattern density, critical dimension, global coordinates and pattern orientation for nanoimprint master manufacturing for the 200 mm wafer scale SmartNIL process

P. Quemere, J. Chartoire, F. Delachat, F. Boudaa, L. Perraud, M. May, H. Teyssedre

Proceedings Volume 10588, 1058807 (2018) https://doi.org/10.1117/12.2299326

KEYWORDS: Semiconducting wafers, Critical dimension metrology, Nanoimprint lithography, Manufacturing, Metrology, Photoresist processing, Silicon, Data modeling, Coating, Scanning electron microscopy

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Proceedings Article | 10 April 2017 Presentation + Paper

Nanoimprint, DSA, and multi-beam lithography: patterning technologies with new integration challenges

S. Landis, H. Teyssedre, G. Claveau, I. Servin, F. Delachat, M. L. Pourteau, A. Gharbi, P. Pimenta Barros, R. Tiron, L. Nouri, N. Possemé, M. May, P. Brianceau, S. Barnola, Y. Blancquaert, J. Pradelles, P. Essomba, A. Bernadac, B. Dal'zotto, S. Bos, M. Argoud, G. Chamiot-Maitral, A. Sarrazin, C. Tallaron, C. Lapeyre, L. Pain

Proceedings Volume 10149, 101490K (2017) https://doi.org/10.1117/12.2259966

KEYWORDS: Directed self assembly, Lithography, Line width roughness, Nanoimprint lithography, Semiconducting wafers, Etching, Electron beam lithography, System on a chip, Critical dimension metrology, Photoresist processing

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