A spectral interferometry technique called vertical travelling scatterometry (VTS) is introduced, demonstrated, and discussed. VTS utilizes unique information from spectral interferometry and enables solutions for applications that are infeasible with traditional scatterometry approaches. The technique allows for data filtering related to spectral information from buried layers, which can then be ignored in the optical model. Therefore, using VTS, selective analyses of the topmost part of an arbitrarily complex stack are possible within a single metrology step. This methodology helps to overcome geometrical complexities and allows for focusing on parameters of interest through dramatically simplified optical modeling. Such model simplifications are specifically desired for back-end-of-line applications. Three examples are monitored discussed: (i) the critical dimensions (CDs) of a first metal level on top of nanosheet gate-all-around transistor structures, (ii) the thickness of an interlayer dielectric above embedded memory in the active area, and (iii) the CDs of trenches on top of tall stacks in the micrometer range comprising many layered dielectrics. It was found that, in all three cases, data filtering through VTS allowed for a simple optical model capable of delivering parameters of interest. The validity and accuracy of the VTS solution results were confirmed by extensive reference metrology obtained by traditional scatterometry, scanning electron microscopy, and transmission electron microscopy. Furthermore, it was shown that machine learning models trained with VTS filtered data can converge to a robust solution with a smaller dataset compared with models training with traditional scatterometry data.
Magnetoresistive random-access memory (MRAM) technology and recent developments in fabrication processes have shown it to be compatible with Si-based complementary metal oxide semiconductor (CMOS) technologies. The perpendicular spin transfer torque MRAM (STT-MRAM) configuration opened up opportunities for an ultra-dense MRAM evolution and was most widely adapted for its scalability. Insertion of STT-MRAM in the back end of line (BEOL) wiring levels has many advantages, including density, latency, and endurance with the promise of being comparable to performance of dynamic random access memory technology (DRAM). There are several important parameters at multiple process steps which require precise metrology for STT-MRAM integration. Inline metrology of the magnetic tunnel junction (MTJ) pillar is vital to calibrate the magnetic read/write performance parameters. This work discusses various challenges to monitor critical process steps for integrating STT-MRAM in advanced CMOS technologies and key metrology solutions are presented. To precisely predict MRAM junction resistance early in the process flow, a machine learning model was developed using scatterometry spectra collected after MTJ pillar formation and corresponding resistance data from the end of line electrical test. This machine learning model utilizes metrology data from the pillar formation process and can predict accurate device resistance values. Additionally, carefully monitoring the required planarization process of an interlayer dielectric deposited after the MTJ pillar formation is critical to avoid subsequent defects. Several modelling techniques are discussed and a new spectral interferometry-based technique, vertical travelling scatterometry (VTS), is demonstrated as a solution for measurements on fully integrated device areas.
KEYWORDS: Metrology, Semiconducting wafers, Scatterometry, Optical filters, Dielectrics, Data modeling, Back end of line, Front end of line, Chemical mechanical planarization, Transmission electron microscopy
In this work, a novel spectral interferometry technique called vertical travelling scatterometry (VTS) is introduced, demonstrated, and discussed. VTS utilizes unique information from spectral interferometry and enables solutions for applications that are infeasible with traditional scatterometry approaches. The technique allows for data filtering related to spectral information from buried layers, which can then be ignored in the optical model. Therefore, using VTS, selective measurements of the topmost part of an arbitrarily complex stack are possible within a single metrology step. This methodology helps to overcome geometrical complexities and allows focusing on parameters of interest through dramatically simplified optical modelling. Such model simplifications are specifically desired for back-end-of-line applications. Three examples are discussed in this paper: monitoring (i) critical dimensions of a first metal level on top of nanosheet gate-all-around transistor structures, (ii) the thickness of an interlayer dielectric above embedded memory in the active area, and (iii) critical dimensions of trenches on top of tall stacks in the micrometer range comprising many layered dielectrics. It was found that, in all three cases, data filtering through VTS allowed for a simple optical model capable of delivering parameters of interest. The validity and accuracy of the VTS solution results were confirmed by extensive reference metrology obtained by traditional scatterometry, scanning electron microscopy, and transmission electron microscopy.
Emerging memory devices, such as MRAM, RRAM, and PCM, plays an important role in in-memory computation technology which can lead to significant acceleration for machine learning and AI applications.[1-3] The basic structure of these memory cell is simply a pillar made of a wide range of materials, however, the local CD uniformity (LCDU) of the pillars is especially crucial for these memory devices. The stringent LCDU requirement derives from either the intrinsic small resistance difference between the two memory states or the requirement for creating a large number of memory states within a small range of resistance. Apparently, the stochastic variation in physical dimension will correspond to the variation in resistance from cell to cell, which will affect the correct readout of the memory states and fail the device.
Because the “local” CDU in this context refers to the variation within the memory array, i.e. typically within several um, it is almost impossible to correct by utilizing existing advanced tools or process control techniques. In this work, we will demonstrate four promising options to address the stochastic effect in LCDU of pillars: a) adopting new resists, b) PTD and NTD shrink, c) DSA, d) cross-SADP. Fig. 1 shows the general approach to achieve better LCDU by printing larger CD at litho and shrink by post-litho processing.[4] Here we carefully characterize two shrinking techniques and its efficacy on LCDU improvement. Fig. 2 shows two alternative approaches, i.e. DSA and cross-SADP.[5] We will carefully explore these four approaches for LCDU improvement with thorough characterization and analysis. Subsequent pattern transfer and the retention of the LCDU improvement and cost/quality trade-off will also be discussed. Defectivity learning will also be discussed.
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