Mr. Pavan K. Samudrala Profile

Pavan K. Samudrala

Scanner Application Engineer at GLOBALFOUNDRIES Inc

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Publications (11)

Proceedings Article | 20 March 2018 Presentation + Paper

Overlay control for 7nm technology node and beyond

Nyan Aung, Woong Jae Chung, Pavan Samudrala, Haiyong Gao, Wenle Gao, Darius Brown, Guanchen He, Bono Park, Michael Hsieh, Xueli Hao, Yen-Jen Chen, Yue Zhou, DeNeil Park, Karsten Gutjahr, Ian Krumanocker, Kevin Jock, Juan Manuel Gomez

Proceedings Volume 10587, 105870A (2018) https://doi.org/10.1117/12.2295828

KEYWORDS: Overlay metrology, Semiconducting wafers, Optical alignment, Reticles, High volume manufacturing, Metrology, HVAC controls, Optimization (mathematics), Scanners, Extreme ultraviolet

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Proceedings Article | 24 March 2017 Presentation + Paper

Mix-and-match considerations for EUV insertion in N7 HVM

Xuemei Chen, Allen Gabor, Pavan Samudrala, Sheldon Meyers, Erik Hosler, Richard Johnson, Nelson Felix

Proceedings Volume 10143, 101430F (2017) https://doi.org/10.1117/12.2258674

KEYWORDS: Extreme ultraviolet, Overlay metrology, Extreme ultraviolet lithography, Distortion, Control systems, Scanners, Imaging systems, Photomasks, Systems modeling, Error analysis, Semiconducting wafers, Reticles, Metrology

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Proceedings Article | 24 March 2017 Paper

Novel methodology to optimize wafer alignment to enhance 14nm on product overlay

Pavan Samudrala, Woong Jae Chung, Lokesh Subramany, Haiyong Gao, Nyan Aung, Seung Chul Oh, Shawn Lee, Erik Delvigne, Blandine Minghetti

Proceedings Volume 10147, 101471U (2017) https://doi.org/10.1117/12.2258137

KEYWORDS: Optical alignment, Overlay metrology, Scanners, Yield improvement, Lithium, Data modeling, Roads

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Proceedings Article | 24 March 2017 Paper

Alignment solutions on FBEOL layers using ASML scanners

Pavan Samudrala, Gregory Hart, Yen-Jen Chen, Lokesh Subramany, Haiyong Gao, Nyan Aung, Woong Jae Chung, Blandine Minghetti, Rajan Mali, Seva Khikhlovskyi, Pieter Heres

Proceedings Volume 10147, 101471T (2017) https://doi.org/10.1117/12.2258128

KEYWORDS: Optical alignment, Sensors, Scanners, Aluminum, Near infrared, Laser beam diagnostics

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Proceedings Article | 21 April 2016 Paper

Analysis of wafer heating in 14nm DUV layers

Lokesh Subramany, Woong Jae Chung, Pavan Samudrala, Haiyong Gao, Nyan Aung, Juan Manuel Gomez, Blandine Minghetti, Shawn Lee

Proceedings Volume 9778, 97780U (2016) https://doi.org/10.1117/12.2218724

KEYWORDS: Semiconducting wafers, Overlay metrology, Deep ultraviolet, Scanners, Process control, Photomasks, Reticles, Metrology, Metals, Data modeling, Image enhancement

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Proceedings Article | 24 March 2016 Paper

Focus control enhancement and on-product focus response analysis methodology

Young Ki Kim, Yen-Jen Chen, Xueli Hao, Pavan Samudrala, Juan-Manuel Gomez, Mark Mahoney, Ferhad Kamalizadeh, Justin Hanson, Shawn Lee, Ye Tian

Proceedings Volume 9778, 97780T (2016) https://doi.org/10.1117/12.2213019

KEYWORDS: Error analysis, High volume manufacturing, Semiconducting wafers, Metrology, Process control, Control systems, Scanners, Diffraction, Time metrology, Forward error correction, Lithography, Critical dimension metrology

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Proceedings Article | 18 March 2016 Paper

Advanced overlay: sampling and modeling for optimized run-to-run control

Lokesh Subramany, WoongJae Chung, Pavan Samudrala, Haiyong Gao, Nyan Aung, Juan Manuel Gomez, Karsten Gutjahr, DongSuk Park, Patrick Snow, Miguel Garcia-Medina, Lipkong Yap, Onur Nihat Demirer, Bill Pierson, John Robinson

Proceedings Volume 9778, 97782K (2016) https://doi.org/10.1117/12.2218729

KEYWORDS: Semiconducting wafers, Data modeling, Overlay metrology, Metrology, Process control, Scanners, Mathematical modeling, High volume manufacturing

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In recent years overlay (OVL) control schemes have become more complicated in order to meet the ever shrinking margins of advanced technology nodes. As a result, this brings up new challenges to be addressed for effective run-to- run OVL control. This work addresses two of these challenges by new advanced analysis techniques: (1) sampling optimization for run-to-run control and (2) bias-variance tradeoff in modeling. The first challenge in a high order OVL control strategy is to optimize the number of measurements and the locations on the wafer, so that the “sample plan” of measurements provides high quality information about the OVL signature on the wafer with acceptable metrology throughput. We solve this tradeoff between accuracy and throughput by using a smart sampling scheme which utilizes various design-based and data-based metrics to increase model accuracy and reduce model uncertainty while avoiding wafer to wafer and within wafer measurement noise caused by metrology, scanner or process. This sort of sampling scheme, combined with an advanced field by field extrapolated modeling algorithm helps to maximize model stability and minimize on product overlay (OPO). Second, the use of higher order overlay models means more degrees of freedom, which enables increased capability to correct for complicated overlay signatures, but also increases sensitivity to process or metrology induced noise. This is also known as the bias-variance trade-off. A high order model that minimizes the bias between the modeled and raw overlay signature on a single wafer will also have a higher variation from wafer to wafer or lot to lot, that is unless an advanced modeling approach is used. In this paper, we characterize the bias-variance trade off to find the optimal scheme. The sampling and modeling solutions proposed in this study are validated by advanced process control (APC) simulations to estimate run-to-run performance, lot-to-lot and wafer-to- wafer model term monitoring to estimate stability and ultimately high volume manufacturing tests to monitor OPO by densely measured OVL data.

Proceedings Article | 15 March 2016 Paper

CDU budget breakdown as a diagnostic method for imaging sensitivity in HVM

Young Ki Kim, Pavan Samudrala, Juan-Manuel Gomez, Peter Nikolsky, Roy Anunciado, Maria Barkelid, Shawn Lee, Ye Tian, Justin Hanson

Proceedings Volume 9780, 97801Q (2016) https://doi.org/10.1117/12.2214123

KEYWORDS: Semiconducting wafers, Reticles, Critical dimension metrology, Scanners, Photomasks, Metrology, Laser processing, Laser scanners, 3D scanning, Laser metrology

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Proceedings Article | 8 March 2016 Paper

Overlay optimization for 1x node technology and beyond via rule based sparse sampling

Nyan Aung, Woong Jae Chung, Lokesh Subramany, Shehzeen Hussain, Pavan Samudrala, Haiyong Gao, Xueli Hao, Yen-Jen Chen, Juan-Manuel Gomez

Proceedings Volume 9778, 97782G (2016) https://doi.org/10.1117/12.2218161

KEYWORDS: Overlay metrology, Metrology, Process control, Statistical modeling, Semiconducting wafers, Scanners, Data centers, MATLAB, Manganese, Semiconductor manufacturing, High volume manufacturing

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Proceedings Article | 8 March 2016 Paper

Comparison study of diffraction based overlay and image based overlay measurements on programmed overlay errors

Haiyong Gao, Woong Jae Chung, Nyan Aung, Lokesh Subramany, Pavan Samudrala, Juan-Manuel Gomez

Proceedings Volume 9778, 97782Q (2016) https://doi.org/10.1117/12.2218163

KEYWORDS: Overlay metrology, Metrology, Diffraction, Process control, Lithography, Semiconductor manufacturing, Error analysis, Reticles, Semiconducting wafers

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Proceedings Article | 8 March 2016 Paper

Scanner baseliner monitoring and control in high volume manufacturing

Pavan Samudrala, Woong Jae Chung, Nyan Aung, Lokesh Subramany, Haiyong Gao, Juan-Manuel Gomez

Proceedings Volume 9778, 977838 (2016) https://doi.org/10.1117/12.2218162

KEYWORDS: Overlay metrology, Scanners, Data modeling, High volume manufacturing, Process control, Manufacturing, Performance modeling, Metrology, Statistical modeling

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Showing 5 of 11 publications

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