Extreme ultraviolet (EUV) technology enables further downscaling for logic and memory designs. This powerful technology comes with new challenges that must be controlled to unlock the novel technology accuracy and capabilities. Freeform (curvilinear) masks introduce a flexible tape-out capability that enables customers to realize EUV technology accuracy and capabilities on wafer. However, the accuracy enhancements of curvilinear masks do not come free of challenges. Source optimization, optical proximity correction (OPC) and verification runtime, mask proximity correction (MPC) runtime, data volume handling at fracture, and finally mask writing time are some of these challenges. In this paper, we present an affordable runtime tape-out flow for optical proximity correction and verification. This tapeout flow connects the capabilities of different engines to balance accuracy and mask turnaround time. Combining the benefits of rigorous solvers and pattern matching with affordable OPC, mask rule check (MRC) and verification capabilities cut down mask turnaround time from weeks to days, offering customers cutting edge technology on wafers with acceptable runtime. In this paper, we present a new flow for EUV freeform OPC with demonstrated runtime and accuracy benefits validated on wafer
With the adoption of extreme ultraviolet (EUV) lithography for high-volume production of advanced nodes, stochastic variability and resulting failures, both post litho and post etch, have drawn increasing attention. There is a strong need for accurate models for stochastic edge placement error (SEPE) with a direct link to the induced stochastic failure probability (FP). Additionally, to prevent stochastic failure from occurring on wafers, a holistic stochastic-aware computational lithography suite of products is needed, such as stochastic-aware mask source optimization (SMO), stochastic-aware optical proximity correction (OPC), stochastic-aware lithography manufacturability check (LMC), and stochastic-aware process optimization and characterization. In this paper, we will present a framework to model both SEPE and FP. This approach allows us to study the correlation between SEPE and FP systematically and paves the way to directly correlate SEPE and FP. Additionally, this paper will demonstrate that such a stochastic model can be used to optimize source and mask to significantly reduce SEPE, minimize FP, and improve stochastic-aware process window. The paper will also propose a flow to integrate the stochastic model in OPC to enhance the stochastic-aware process window and EUV manufacturability.
With the adoption of extreme ultraviolet (EUV) lithography for high volume production in the advanced wafer manufacturing fab, defects resulting from stochastic effects could be one of major yield killers and draw increasing interest from the industry. In this paper, we will present a flow, including stochastic edge placement error (SEPE) model calibration, pattern recognition and hot spot ranking from defect probability, to detect potential hot spot in the chip design. The prediction result shows a good match with the wafer inspection. HMI eP5 massive metrology and contour analysis were used to extract wafer statistical edge placement distribution data.
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