Field-effect transistors (FETs) with channels of two-dimensional transition metal dichalcogenides (2D TMDs) are expected to extend Moore’s law by extreme scaling of contacted gate pitch (CGP) post silicon-sheet-based complementary FET (CFET) devices. The ultrathin body and fully passivated surface of 2D materials result in superior electrostatic control and improved short channel behavior. Challenges such as high contact resistance or lack of doping technology are on the way of 2D-FETs reaching the required performance for high-performance logic applications. Additionally, in order to integrate 2D TMDs in ultra-scaled CMOS devices, developing a patterning scheme via the state-of-the-art extreme ultraviolet (EUV) lithography is essential. In this paper we demonstrate our first results on studying the compatibility and interaction of semiconducting 2D TMDs with EUV environment using a set of characterization techniques that are fit to detect qualitative defects and morphological changes in these atomically thin layers. Our study is focused on semiconducting TMDs that are currently the most promising candidates for transistor channels: MoS2 (NMOS) and WSe2 (PMOS). We report the interaction of EUV photons and photo-electrons with blanket films of MoS2 and WSe2 for different EUV doses in vacuum environment. Based on the current findings we propose design of experiments aiming at developing controllable and tunable modification and patterning of 2D TMDs with the EUV energy and resolution for advanced device nodes.
In order to improve logic via printing we propose staggered vias to effectively regularize randomly placed vias in a typical logic design. We accomplish this (i) by forcing via placement on a staggered sub-grid of the standard manhattan grid and (ii) by placing smaller fixed-size via Sub-Resolution Assist Features (SRAFs) on all remaining empty positions of the staggered grid. We devised a methodology to create such staggered via placement in a standard Place&Route (PNR) design flow and evaluated the concept on a 64-bit (64b) ARM core implementation through a PowerPerformance-Area (PPA) analysis. From a PNR run-time perspective and PPA analysis this looked a very viable implementation with little to no disadvantages compared to standard via placement. Finally, to experimentally test and compare staggered vias and against standard manhattan vias, we designed a via mask with both staggered and standard manhattan vias patterns and exposed them on an 0.33NA NXE3400 EUV lithography system. Analysis of experimental results on a 38nm via pitch show 40% smaller best-focus shift across the slit, and 20% smaller via-via CD variation for staggered vias compared to Manhattan vias with regular SMO.
Anamorphic imaging enables NA=0.55 in future EUV systems. At unchanged reticle size, the maximum on-wafer image size is reduced from the today’s full-field to a half-field of 26mm by16.5mm. Though most of the applications use a chip smaller than a half field, some of them still need a larger chip. To realize an on-wafer full-field with an NA=0.55 EUV system, two half-field images need to be stitched: abutting two images from a single reticle or from two different reticles, depending on the application. Using the ASML NA=0.33 NXE system at imec, “at-resolution stitching” on wafer is used to explore experimentally how CD and pattern placement are affected by abutting images of critical patterns located at the reticle edge. Using various test masks, a pattern placement error is measured within a 10μm range (1x) from the Black Border (BB) edge. Ideally it will be avoided by an adequate mask manufacturing process. We also measure a crosstalk between the two abutting images, that is attributed to a flare crosstalk, impacting the CD of critical patterns. Dummy tiles and a flare OPC need to compensate for this effect similarly to the correction inside the image. Finally, at short range, aerial images of the critical patterns at the very edge of abutting images can crosstalk. To avoid a complex OPC and tight specifications on the BB edge, an exclusion band is recommended to keep those aerial images from interacting. With the adequate placement solution at mask BB edge and with a flare compensation solution implemented, an exclusion band of about 1μm at wafer level is sufficient to support a robust stitching scenario for anamorphic High NA imaging. Its impact on various types of applications is discussed.
We explore various resolution enhancement techniques and investigate their patterning benefits for via patterns of the 3-nm logic node using computational lithography. Simulations are performed by the method of source mask optimization (SMO) using the TachyonTM software. Key assessed process parameters include edge placement error (EPE), overlap process window, image NILS, local CD uniformity and NILS depth of focus (nDOF). Simulation results show that the current mask technology employing the standard Ta-based metallic absorber does not offer enough patterning performance for vias of pitch 40 nm and below. SMO results indicate that high-absorption absorbers give a clear improvement in best-focus shift and pattern placement error while phase-shift masks result in a significant increase of NILS and nDOF. EPE improvement of multiple technologies are also investigated. Novel EUV masks together with advanced imaging with low pupil-filling ratio and curvilinear OPC, combined with highresolution and low-roughness resist and enhanced etch process are among the key enabling technologies to extend EUV single patterning to 3-nm logic via layers.
The most exciting and continuous debate in our industry is how long Moore’s law will continue, and tightly connected
to this is the discussion on when EUV Lithography will be introduced in microchip mass manufacturing.
In this review paper, we analyze and extrapolate Moore’s law based on critical design pitches for Logic and Memory
devices. We will focus in more detail on an aggressive option for the 7nm Logic node based on an extrapolation in
accordance with Moore’s law. For this node, we will discuss and compare all-immersion vs immersion-EUV based litho
manufacturing costs, complexity and restrictions and consolidate field expert statements on device performance tradeoffs.
We will conclude with an outlook on the affordability of shrink based on node-on-node CapEx projections.
Based on interactions with our customers and peers, we project Moore’s law to continue in the 2020s, and we predict
that shrink will remain profitable. Manufacturing cost and complexity will be mitigated by the introduction of EUV
lithography. The recent progress in EUV productivity will ensure cost effectiveness of EUV-based designs, creating a
“sweet spot” for EUV introduction at the 7nm node.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.