Dr. Qiaowei Lou Profile

Dr. Qiaowei Lou

at TEL Technology Ctr America LLC

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Publications (3)

SPIE Journal Paper | 17 June 2021

Line edge roughness reduction for EUV self-aligned double patterning by surface modification on spin-on-carbon and tone inversion technique

Eric Liu, Katie Lutker-Lee, Qiaowei Lou, Ya-Ming Chen, Angélique Raley, Peter Biolsi, Kai-Hung Yu, Gregory Denbeaux

JM3, Vol. 20, Issue 02, 024901, (June 2021) https://doi.org/10.1117/12.10.1117/1.JMM.20.2.024901

KEYWORDS: Line edge roughness, System on a chip, Extreme ultraviolet, Plasma, Etching, Lithography, Silicon, Double patterning technology, Line width roughness, Extreme ultraviolet lithography

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Extreme ultraviolet lithography (EUVL) has been adopted into high volume production for advanced logic device manufacturing. Due to the continuous size scaling requirement for interconnect fabrication, EUVL with self-aligned double patterning (SADP) formation has attracted substantial research attention. The current challenge in EUV SADP is the pattern transfer process from lithography to mandrel formation. In this step, the target critical dimension (CD) of the feature needs to shrink by half from the lithography CD during the etch process. The increasing aspect ratio during this etch potentially deteriorates the pattern validity and the line edge roughness (LER). In addition to these challenges, EUVL has a fundamental bottleneck due to stochastic effects, which can lead to device degradation by defect formation and edge placement error (EPE). LER of the line and space pattern is one of the main contributors to EPE. Effective methods of LER reduction in both process and integration are needed in order to reduce pattern variation and boost device performance. In our study, we examine a technique to reduce LER on the EUV SADP line pattern. This technique involves the surface modification on the spin-on carbon (SOC) layer in the patterning stack and tone inversion process. We had found a trend between surface hydrophobicity of the SOC and the EUV SADP LER performance. The condition that increased the hydrophobicity of the SOC resulted in a lower LER performance after tone inversion. The tested conditions include direct current superposition (DCS) function with H2 plasma, fluorocarbon plasma, and the combination of DCS with H2 plasma and trimethylsilane dimethylamine deposition. On 20-nm pitch EUV SADP, this technique shows 26% of LER improvement from lithography to SADP formation. PSD analysis recorded about 6% and 30% of the LER improvement at the correlation length of >200 nm and 200 to 30 nm, respectively. A demonstration of this technique for a further scaling to 15-nm pitch also shows an LER reduction of 30% from lithography to SADP formation.

Proceedings Article | 9 April 2021 Presentation + Paper

Line edge roughness (LER) reduction strategies for EUV self-aligned double patterning (SADP)

Eric Liu, Katie Lutker-Lee, Qiaowei Lou, Ya-Ming Chen, Angélique Raley, Peter Biolsi

Proceedings Volume 11615, 1161506 (2021) https://doi.org/10.1117/12.2582556

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Extreme ultraviolet lithography (EUVL) has been adopted into high volume production for advanced logic device manufacturing. Due to the continuous size scaling requirement for interconnect fabrication, EUVL with self-aligned double patterning (SADP) formation has attracted substantial research attention [1]–[6]. Double patterning techniques in EUVL achieve pitch halving in the final feature by using the spacer defined approach and self-aligned block (SAB) mitigates the block placement error by leveraging etch selectivities and material filling capability. The current challenge in EUV SADP is the pattern transfer process from lithography to mandrel formation. In this step, the target critical dimension (CD) of the feature needs to shrink by half from the lithography CD during the etch process. The increasing aspect ratio during this etch potentially deteriorates the pattern validity and the line edge roughness (LER) [5]. In addition to these challenges, EUVL has a fundamental bottleneck due to stochastic effects which can lead to device degradation by defect formation and edge-placement-error (EPE) [7]–[10]. LER of the line and space pattern is one of the main contributors to EPE. Effective methods of LER reduction in both process and integration are needed in order to reduce pattern variation and boost device performance. In our research, we examine three approaches to reduce LER on the EUV SADP line pattern. This includes photoresist surface smoothing techniques, patterning layer material study, and tone inversion integration. The photoresist surface smoothing techniques involve a specific plasma process on the EUV chemical amplified resist (CAR) to achieve > 15% of improvement on LER from lithography to post etch performance. The patterning layer material study reveals an optimum patterning stack to minimize etch-induced line wiggling and etch selectivity requirements for LER performance. Finally, a first demonstration of EUV SADP tone inversion process integration is presented as a method to provide additional benefits to LER reduction. A detailed analysis of line performance from each processing step will be examined.

Proceedings Article | 6 April 2020 Presentation + Paper

Strategies for aggressive scaling of EUV multi-patterning to sub-20 nm features

Ashim Dutta, Jennifer Church, Joe Lee, Brendan O’Brien, Luciana Meli, Chi Chun Liu, Saumya Sharma, Karen Petrillo, Cody Murray, Eric Liu, Katie Lutker-Lee, Qiaowei Lou, Chris Cole, Angélique Raley, Akiteru Ko, Subhadeep Kal, Jake Kaminsky, Aelan Mosden, Henan Zhang, Shan Hu, Lior Huli, Naoki Shibata, Dave Hetzer, Chia-Yun (Sharon) Hsieh

Proceedings Volume 11323, 113230V (2020) https://doi.org/10.1117/12.2551727

KEYWORDS: Line edge roughness, Lithography, Etching, Amorphous silicon, Extreme ultraviolet, Oxidation, Extreme ultraviolet lithography, Optical lithography, Scanning electron microscopy, Critical dimension metrology

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