We present an on-chip LED based on native Si, fabricated in an open foundry CMOS node. This LED has remarkable characteristics such as its sub-wavelength emission area, broad spectrum, high spatial intensity, high bandwidth, and high reproducibility, which make it an ideal light source for various imaging and sensing systems. Two prototypes, a holographic microscope and a LIDAR, are built employing this LED. Our work demonstrates the possibility of integrating monolithic light sources with other photonic and electronic components on a single photonic chip.
Scalable, low power, high speed data transfer between cryogenic and room temperature environments is essential for the realization of practical, large-scale systems based on superconducting technologies. Optical fiber presents a 100–1,000x lower heat load than conventional electrical wiring, relaxing the requirements for thermal anchoring, and allows for very high bandwidth densities by carrying multiple signals through the same physical fiber. By operating a CMOS modulator in the forward bias regime at a temperature of 3.6 K, we have demonstrated the optical readout of a superconducting nanowire single-photon detector (SNSPD) without the need for an interfacing device.
The last 36 years has seen a steady increase in the deployment of photonic integrated components. Over most of this history, the development of integrated photonic systems in both III-V and Group IV materials has been driven by the needs of fibre optic systems – driven primarily by the properties of the transmission media (single-mode vs multi-mode fibre, fibre gain, etc). Today, photonic integration is increasingly driven by the unique properties of high-performance electronic-photonic interfaces. The low-capacitance, low-energy, high-bandwidth density of photonic integrated systems is now driving optical interconnection into board-scale, chip-scale, and intra-chip photonic systems.
Here, we consider new applications ranging from (1) deep learning systems and other data intensive classical compute applications, (2) optically addressed quantum computing fabrics – with tremendous progress being made today in the area of trapped-ion quantum computing, and (3) next-generation brain-computer interfaces where photonics may play an important role in massively parallel signal detection.
Silicon technologies have been developed for both electronics and photonics. Future demands call for further innovation in each field separately, but also depend on our ability to bring the best of both worlds together through integrated solutions. For decades, the pursuit of all-silicon electronic-photonic integration has been hindered by the lack of a native light source due to silicon’s indirect bandgap. Here, we discuss the potential for micro- and nano-scale light sources realized in microelectronic CMOS technology without any modification or postprocessing. High brightness is realized by exploiting the well-passivated silicon surfaces available in CMOS to realize efficient light emission despite the indirect bandgap. NIR emission at the silicon bandgap is demonstrated and exploited to demonstrate chip-to-chip optical links and sensors utilizing only silicon light sources.
Single-photon avalanche diodes (SPADs) must be integrated on modern highly-scaled process nodes to achieve high array fill factors and imager pixel counts. Integration also enables applications where rapid, complex data processing needs to be co-located with these detectors and other photonic components. In this work we implement 5μm, 10μm, and 15μm-diameter circular SPADs using a p+/n-well structure and an STI guard ring in a 90nm bulk CMOS process, and in contrast to previous work on silicon SPADs carry out detailed study of dark count rate (DCR) and afterpulsing at cryogenic temperatures. With passive quenching these SPADs are saturated by dark counts at room temperature and by afterpulsing at cryogenic temperatures, motivating the development of an active quenching circuit (AQC) to characterize and ultimately suppress the processes responsible for these non-idealities. A novel AQC topology based on a linear output stage, able to detect avalanches and drive SPADs connected by a coaxial cable faster than previously-demonstrated circuits, is proposed and demonstrated. This circuit enables device testing using a coaxial microprobe inside a Helium cryostat. To quantify the SPADs’ performance, we operate them in free-running mode and collect histograms of the pulse interarrival times from which we extract the DCR and afterpulsing probability. We use this technique to measure these parameters with varying temperature and overbias voltage, showing there is an optimal temperature for operating each SPAD. With active quenching we achieve 100Hz-level DCR, <10% afterpulsing probability, >10% 405nm quantum efficiency at 140K, and are presently characterizing the photon detection probability.
As the best performing light emitting diodes (LEDs) are approaching the conventional limit of unity efficiency, a unique heat-pump operating mode of the devices has been proposed to address this problem, in which case lattice heat is pumped from the phonon field of the device into the incoherent photon field of emission at the expense of consuming zero-entropy electrical power. To better understand the potential of visible LEDs for further efficiency improvement in this mode, we present a thermodynamic framework that allows us to estimate the Carnot limit for their wall-plug efficiency (WPE) at different operating conditions. We find that the theoretical efficiency limit drops at higher light intensities but can still be well above 100% even at 10 W/cm^2. Ideally, realizing such high efficiency at useful output powers requires the device to possess an external quantum efficiency (EQE) close to unity. Here we are able to introduce dissipation into the thermodynamic model and thus determine a minimum EQE required for an LED to achieve unity WPE. In addition, the thermodynamic study for visible LEDs yields one surprising result. The first observation of above-unity WPE was on a heated mid-infrared (2.2 um) LED, and the subsequent demonstration at room temperature necessarily required a longer-wavelength 3.4 um device in order to realize sufficient carrier injection for measurable optical output. On the contrary, this thermodynamic analysis indicates that at useful optical powers – and hence useful cooling powers – visible LEDs of shorter wavelength are expected to show higher cooling at a lower current density.
It is known that the wall-plug efficiency (WPE) of a light-emitting diode (LED) can exceed unity and that electroluminescence cooling (ELC) happens in this scenario. However, it is difficult to observe the associated temperature drop due to the relatively small cooling power and the overwhelming heat flux from the ambient. In this work, we design a photonic crystal (PhC) enhanced LED which has smaller surface area as well as thermal mass compared with an encapsulated LED. We also present thermal models to evaluate the temperature drop of the LED in air and vacuum.
The wall-plug efficiency of modern light-emitting diodes (LEDs) has far surpassed all other forms of lighting and is expected to improve further as the lifetime cost of a luminaire is today dominated by the cost of energy. The drive towards higher efficiency inevitably opens the question about the limits of future enhancement. Here, we investigate thermoelectric pumping as a means for improving efficiency in wide-bandgap GaN based LEDs. A forward biased diode can work as a heat pump, which pumps lattice heat into the electrons injected into the active region via the Peltier effect. We experimentally demonstrate a thermally enhanced 450 nm GaN LED, in which nearly fourfold light output power is achieved at 615 K (compared to 295 K room temperature operation), with virtually no reduction in the wall-plug efficiency at bias V < ℏω/q. This result suggests the possibility of removing bulky heat sinks in high power LED products. A review of recent high-efficiency GaN LEDs suggests that Peltier thermal pumping plays a more important role in a wide range of modern LED structures that previously thought – opening a path to even higher efficiencies and lower lifetime costs for future lighting.
Here, I review the development of a polysilicon photonic platform that is optimized for integration with electronics fabricated on bulk silicon wafers. This platform enables large-scale monolithic integration of silicon photonics with microelectronics. A single-polysilicon deposition and lithography mask were used to simultaneously define the transistor gate, the low-loss waveguides, the depletion modulators, and the photodetectors. Several approaches to reduce optical scattering and mitigate defect state absorption are presented. Waveguide propagation loss as low as 3 dB/cm could be realized in front-end polysilicon with an end-of-line loss as low as 10 dB/cm at 1280nm. The defect state density could be enhanced to enable all-silicon, infrared photodetectors. The resulting microring resonant detectors exhibit over 20% quantum efficiency with 9.7 GHz bandwidth over a wide range of wavelengths. A complete photonic link has been demonstrated at 5 Gbps that transfers digital information from one bulk CMOS photonics chip to another.
We review recent progress of an effort led by the Stojanović (UC Berkeley), Ram (MIT) and Popović (CU Boulder) research groups to enable the design of photonic devices, and complete on-chip electro-optic systems and interfaces, directly in standard microelectronics CMOS processes in a microprocessor foundry, with no in-foundry process modifications. This approach allows tight and large-scale monolithic integration of silicon photonics with state-of-the-art (sub-100nm-node) microelectronics, here a 45nm SOI CMOS process. It enables natural scale-up to manufacturing, and rapid advances in device design due to process repeatability. The initial driver application was addressing the processor-to-memory communication energy bottleneck. Device results include 5Gbps modulators based on an interleaved junction that take advantage of the high resolution of the sub-100nm CMOS process. We demonstrate operation at 5fJ/bit with 1.5dB insertion loss and 8dB extinction ratio. We also demonstrate the first infrared detectors in a zero-change CMOS process, using absorption in transistor source/drain SiGe stressors. Subsystems described include the first monolithically integrated electronic-photonic transmitter on chip (modulator+driver) with 20-70fJ/bit wall plug energy/bit (2-3.5Gbps), to our knowledge the lowest transmitter energy demonstrated to date. We also demonstrate native-process infrared receivers at 220fJ/bit (5Gbps). These are encouraging signs for the prospects of monolithic electronics-photonics integration. Beyond processor-to-memory interconnects, our approach to photonics as a “More-than- Moore” technology inside advanced CMOS promises to enable VLSI electronic-photonic chip platforms tailored to a vast array of emerging applications, from optical and acoustic sensing, high-speed signal processing, RF and optical metrology and clocks, through to analog computation and quantum technology.
We present the spoked-ring microcavity, a nanophotonic building block enabling energy-efficient, active photonics in
unmodified, advanced CMOS microelectronics processes. The cavity is realized in the IBM 45nm SOI CMOS process –
the same process used to make many commercially available microprocessors including the IBM Power7 and Sony
Playstation 3 processors. In advanced SOI CMOS processes, no partial etch steps and no vertical junctions are available,
which limits the types of optical cavities that can be used for active nanophotonics. To enable efficient active devices
with no process modifications, we designed a novel spoked-ring microcavity which is fully compatible with the
constraints of the process. As a modulator, the device leverages the sub-100nm lithography resolution of the process to
create radially extending p-n junctions, providing high optical fill factor depletion-mode modulation and thereby
eliminating the need for a vertical junction. The device is made entirely in the transistor active layer, low-loss crystalline
silicon, which eliminates the need for a partial etch commonly used to create ridge cavities. In this work, we present the
full optical and electrical design of the cavity including rigorous mode solver and FDTD simulations to design the Qlimiting
electrical contacts and the coupling/excitation. We address the layout of active photonics within the mask set of
a standard advanced CMOS process and show that high-performance photonic devices can be seamlessly monolithically
integrated alongside electronics on the same chip. The present designs enable monolithically integrated optoelectronic
transceivers on a single advanced CMOS chip, without requiring any process changes, enabling the penetration of
photonics into the microprocessor.
Silicon is considered a promising platform for photonic integrated circuits as they can be fabricated in state-of-the-art
electronics foundaries with integrated CMOS electronics. While much of the existing work on CMOS photonics has
used directional couplers for power splitting, multimode interference (MMI) devices may have relaxed fabrication
requirements and smaller footprints, potentially energy efficient designs. They have already been used as 1x2 splitters,
2x1 combiners in Quadrature Phase Shift Keying modulators, and 3-dB couplers among others. In this work, 3-dB,
butterfly and cross MMI couplers are realized on bulk CMOS technology. Footprints from around 40um2 to 200 um2 are obtained. MMI tolerances to manufacturing process and bandwidth are analyzed and tested showing the robustness of the MMI devices.
Front-end monolithic integration has enabled photonic devices to be fabricated in bulk and thin-SOI
CMOS as well as DRAM electronics processes. Utilizing the CMOS generic process model,
integration was accomplished on multi-project wafers that were shared by standard electronic
customers without requiring in-foundry process changes. Simple die or wafer-level post-processing
has enabled low-loss waveguides by the removal of the substrate within photonic regions. The
custom-process model of the DRAM industry instead enabled optimization of the photonic device
fabrication process and the potential elimination of post-processing requirements. Integrated singlecrystalline
silicon waveguide loss of ~3 dB/cm has been achieved within a 45nm thin-SOI CMOS
process that is currently used to manufacture microprocessors [1]. A fully monolithic photonic
transmitter including a pseudo-random bit sequence (PRBS) generating digital backend was also
demonstrated within this process [1]. The constraints of zero-change integration have limited
achieved polysilicon waveguide loss to ~50 dB/cm with commercially available bulk CMOS
processes [2]. Custom polysilicon deposition and processing conditions available for DRAM
integration have also led to the demonstration of ~6 dB/cm loss waveguides suitable for integration
within electronics processes utilizing bulk silicon starting substrates [3]. An overview of required
process features, device design guidelines and integration methodology tradeoffs will be presented.
Relevant device metrics of area and energy efficiency as well as achievable photonic device
performance will be presented within the context of monolithic front-end integration within state-ofthe-
art electronics processes. Applications of this research towards the implementation of a
computer system utilizing photonic interconnect for core-to-memory communication will also be
discussed.
Experimental demonstration of net electro-luminescent cooling in a diode, or equivalently electroluminescence with wall-plug efficiency greater than unity, had eluded direct observation for more than five decades. We review experiments demonstrating light emission from a light-emitting diode in which the electron population is pumped by a combination of electrical work and heat.
Sampling rates of high-performance electronic analog-to-digital converters (ADC) are fundamentally limited by the timing jitter of the electronic clock. This limit is overcome in photonic ADC's by taking advantage of the ultra-low timing jitter of femtosecond lasers. We have developed designs and strategies for a photonic ADC that is capable of 40 GSa/s at a resolution of 8 bits. This system requires a femtosecond laser with a repetition rate of 2 GHz and timing jitter less than 20 fs. In addition to a femtosecond laser this system calls for the integration of a number of photonic components including: a broadband modulator, optical filter banks, and photodetectors. Using silicon-on-insulator (SOI) as the platform we have fabricated these individual components. The silicon optical modulator is based on a Mach-Zehnder interferometer architecture and achieves a VπL of 2 Vcm. The filter banks comprise 40 second-order microring-resonator filters with a channel spacing of 80 GHz. For the photodetectors we are exploring ion-bombarded silicon waveguide detectors and germanium films epitaxially grown on silicon utilizing a process that minimizes the defect density.
Photonic Analog-to-Digital Conversion (ADC) has a long history. The premise is that the superior noise performance of
femtosecond lasers working at optical frequencies enables us to overcome the bottleneck set by jitter and bandwidth of
electronic systems and components. We discuss and demonstrate strategies and devices that enable the implementation
of photonic ADC systems with emerging electronic-photonic integrated circuits based on silicon photonics. Devices
include 2-GHz repetition rate low noise femtosecond fiber lasers, Si-Modulators with up to 20 GHz modulation speed,
20 channel SiN-filter banks, and Ge-photodetectors. Results towards a 40GSa/sec sampling system with 8bits resolution
are presented.
Advances in femtosecond lasers and laser stabilization have led to the development of sources of ultrafast optical pulse
trains that show jitter on the level of a few femtoseconds over tens of milliseconds and over seconds if referenced to
atomic frequency standards. These low jitter sources can be used to perform opto-electronic analog to digital conversion
that overcomes the bottleneck set by electronic jitter when using purely electronic sampling circuits and techniques.
Electronic Photonic Integrated Circuits (EPICs) may enable in the near future to integrate such an opto-electronic
analog-to-digital converters (ADCs) completely. This presentation will give an overview of integrated optical devices
such as low jitter lasers, electro-optical modulators, Si-based filter banks, and high-speed Si-photodetectors that are
compatible with standard CMOS processing and which are necessary for the implementation of EPIC-chips for advanced
opto-electronic ADCs.
Magnetically doped Fe:InP and Fe:InGaAsP was characterized for verdict coefficient. The verdet coefficient was measured to be 180°/mm/T for Fe:InGaAsP, which is higher than YIG. High mesa waveguide of Fe doped InP/InGaAsP was fabricated and characterized. Faraday rotation in InP/InGaAsP waveguide was measured for the first time. The measured verdict coefficient is 33.3°/mm/T, which is only four times smaller than that of YIG.
Progress in developing high speed ADC's occurs rather slowly - at a resolution increase of 1.8 bits per decade. This slow progress is mostly caused by the inherent jitter in electronic sampling - currently on the order of 250 femtoseconds in the most advanced CMOS circuitry. Advances in femtosecond lasers and laser stabilization have led to the development of sources of ultrafast optical pulse trains that show jitter on the level of a few femtoseconds over the time spans of typical sampling windows and can be made even smaller. The MIT-GHOST (GigaHertz High Resolution Optical Sampling Technology) Project funded under DARPA's Electronic Photonic Integrated Circuit (EPIC) Program is trying to harness the low noise properties of femtosecond laser sources to overcome the electronic bottleneck inherently present in pure electronic sampling systems. Within this program researchers from MIT Lincoln Laboratory and MIT Campus develop integrated optical components and optically enhanced electronic sampling circuits that enable the fabrication of an electronic-photonic A/D converter chip that surpasses currently available technology in speed and resolution and opens up a technology development roadmap for ADC's. This talk will give an overview on the planned activities within this program and the current status on some key devices such as wavelength-tunable filter banks, high-speed modulators, Ge photodetectors, miniature femtosecond-pulse lasers and advanced sampling techniques that are compatible with standard CMOS processing.
The Faraday effect of magnetically doped Fe:InP with Fe concentration of 3 x 1016 cm-3 doping is characterized. It demonstrates a Verdet coefficient of 23.8 °/cm/T at 1550 nm. For 45°rotation, the insertion loss at this wavelength is 1.66 dB. A zero-birefringence waveguide is designed and fabricated. The loss and birefringence of the waveguide are characterized.
Semiconductor cascade lasers have larger photon noise than conventional single stage semiconductor lasers as a result of positive correlations in photon emission in different gain stages which are connected electrically in series. The photon noise of
cascade lasers can be related to the photon noise of single stage lasers with scaled external circuit impedances. This scaling relation for the photon noise holds for bipolar as well as unipolar cascade lasers.
This paper explores the development of cascade semiconductor lasers for communications applications. Both interband and intersubband cascade emission devices are examined theoretically and experimentally. The motivation for cascade sources in both high fidelity and high bandwidth applications is presented. The ability to transmit signals with lower signal loss and improved noise performance is verified by measurements on a model systems consisting of series coupled DFB lasers.
We propose a new class of intersubband lasers and amplifiers that achieve net gain without population inversion. The laser scheme is based on a unipolar semiconductor double quantum- well structure where gain occurs at a transition between conduction band subbands. In order to achieve net gain without inversion, we utilize Fano-type interferences. The semiconductor laser scheme that we are considering is analogous to the atomic lambda system that has been extensively analyzed in the context of electromagnetically induced transparency and lasing without inversion. A coherent coupling field however, is not required in the present scheme. The electronic coherence necessary for Fano-type interferences is established by resonant tunneling. For nonlinear optics applications, the asymmetry of the structure allows for (chi) (2) processes and therefore higher conversion efficiency or parametric gain.
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