KEYWORDS: Monte Carlo methods, Computer simulations, Tolerancing, 3D modeling, Lithography, Semiconductors, Logic, Performance modeling, Process engineering, Data modeling, Manufacturing, Design for manufacturability, Detection and tracking algorithms, Statistical modeling, Systems modeling
We demonstrate a tool which can function as an interface between VLSI designers and process-technology engineers
throughout the Design-Technology Co-optimization (DTCO) process. This tool uses a Monte Carlo algorithm on the
output of lithography simulations to model the frequency of fail mechanisms on wafer. Fail mechanisms are defined
according to process integration flow: by Boolean operations and measurements between original and derived shapes.
Another feature of this design rule optimization methodology is the use of a Markov-Chain-based algorithm to perform a
sensitivity analysis, the output of which may be used by process engineers to target key process-induced variabilities for
improvement. This tool is used to analyze multiple Middle-Of-Line fail mechanisms in a 10nm inverter design and identify
key process assumptions that will most strongly affect the yield of the structures. This tool and the underlying algorithm
are also shown to be scalable to arbitrarily complex geometries in three dimensions. Such a characteristic which is
becoming more important with the introduction of novel patterning technologies and more complex 3-D on-wafer
structures.
We continue to study the feasibility of using Directed Self Assembly (DSA) in extending optical lithography for High
Volume Manufacturing (HVM). We built test masks based on the mask datatprep flow we proposed in our prior year’s
publication [1]. Experimental data on circuit-relevant fin and via patterns based on 193nm graphoepitaxial DSA are
demonstrated on 300mm wafers. With this computational lithography (CL) flow we further investigate the basic
requirements for full-field capable DSA lithography. The first issue is on DSA-specific defects which can be either
random defects due to material properties or the systematic DSA defects that are mainly induced by the variations of the
guiding patterns (GP) in 3 dimensions. We focus in studying the latter one. The second issue is the availability of fast
DSA models to meet the full-chip capability requirements in different CL component’s need. We further developed
different model formulations that constitute the whole spectrum of models in the DSA CL flow. In addition to the
Molecular Dynamic/Monte Carlo (MD/MC) model and the compact models we discussed before [2], we implement a 2D
phenomenological phase field model by solving the Cahn-Hilliard type of equation that provide a model that is more
predictive than compact model but much faster then the physics-based MC model. However simplifying the model might
lose the accuracy in prediction especially in the z direction so a critical question emerged: Can a 2D model be useful fro
full field? Using 2D and 3D simulations on a few typical constructs we illustrate that a combination of 2D mode with
pre-characterized 3D litho metrics might be able to approximate the prediction of 3D models to satisfy the full chip
runtime requirement. Finally we conclude with the special attentions we have to pay in the implementation of 193nm
based lithography process using DSA.
Due to the absence of defect-free blanks in extreme ultraviolet (EUV) lithography, defect mitigation is necessary
before mass production. One effective way to mitigate the defect impact is to increase the distance between the
defects and feature boundaries such that the defects will not affect the printing of the features. Some algorithms
have been developed to move the whole layout within the exposure field in order to avoid all defect impact.
However, in reality the die size is usually much smaller than the exposure field, such that one blank is packed
with multiple copies of the die, and each die can be placed independently within the exposure field. In this
paper, we develop an EUV reticle placement algorithm to maximize the number of valid dies that are immune
to defects. Given the layout of a die and a defective blank, we first apply a layout relocation algorithm to find
all feasible regions for the die on the blank. Then we develop an efficient placement algorithm to place the dies
within the feasible regions one at a time until all feasible regions are fully occupied. The simulation results show
that our algorithm is able to find a solution efficiently and the number of valid dies placed by our algorithm is
very close to the optimal solution.
Self-aligned quadruple patterning (SAQP) lithography is one of the major techniques for the future process
requirement after 16nm/14nm technology node. In this paper, based on the existing knowledge of current 193nm
lithography and process flow of SAQP, we will process an early study on the definition of SAQP-friendly layout.
With the exploration of the feasible feature regions and possible combinations of adjacent features, we will define
several simple but important geometry rules to help define the SAQP-friendliness. Then, we will introduce a
conflicting graph algorithm to generate the feature region assignment for SAQP decomposition. Our experimental
results validate our SAQP-friendly layout definition, and basic circuit building blocks in the low level metal layer
are analyzed.
Self-aligned double patterning (SADP) lithography is a novel lithography technology which has the capability to
define critical dimension (CD) using one single exposure, therefore holding a great opportunity for the next generation
lithography process for the overlay mitigation. However, a necessary design manufacturing co-optimization
step - the non-decomposability position detection (hot spot detection) - is still immature. In this paper, targeting
the hot spot detection difficulties in SADP process, we first revisit out previous ILP-based SADP decomposition
algorithm and provide an extended ILP-based hot spot detection without any preconditions on the design. Then,
with some simple requirement that is commonly seen in 2D random layout, we further provided a graph based
hot spot detection for an efficient hot spot detection. From the Nangate standard cell library, our experiment
validates the hot spot detection process and demonstrates an SADP friendly design tyle is necessary for the
upcoming 14nm technology node.
Due to the absence of defect-free blanks in extreme ultraviolet (EUV) lithography, defect mitigation is necessary
before mass production. Currently almost all the defect mitigation methods are focused on mitigating the defect
impact of one blank on one design. However, since the EUV mask vendors always have multiple designs and blanks
in hand, it is also very important to consider all designs and blanks together to mitigate the total defect impact.
This paper proposes a new EUV mask preparation strategy which optimally matches a set of defective blanks
with multiple designs to mitigate the total defect impact. In the first step, an efficient layout relocation algorithm
is adopted to minimize the defect impact of each blank on each design. Then, depending on whether blank defects
are allowed to be compensated, we formulate the two different types of design-blank matching problems as flow
problems and solve them optimally. Compared to sequential matching, the proposed simultaneous matching
strategy shows advantages in both blank utilization and defect compensation cost minimization.
We identify most recent sources of transistor layout dependent effects (LDE) such as stress, lithography,
and well proximity effects (WPE), and outline modeling and analysis methods for 28 nm. These methods
apply to custom layout, standard cell designs, and context-aware post-route analysis. We show how IC
design teams can use a model-based approach to quantify and analyze variability induced by LDE. We
reduce the need for guard-bands that negate the performance advantages that stress brings to advanced
process technologies.
Pitch-splitting type of double-patterning lithography is a necessity for critical layers for sub-22 nm technologies.
Double patterning lithography techniques require additional masks to manufacture a single device layer.
Consequently, double-patterning lithography brings overlay as a challenge that introduces additional variability
to gate-to-contact coupling capacitances, device lengths, and contact resistances. These additional variability
sources may negatively impact circuit performance. In this work, we provide analysis of digital and analog
circuit blocks designed in 20 nm. We demonstrate the impact due to overlay-impacted change in resistance of
self-aligned contacts. Furthermore, we provide layout optimization guidelines to reduce the impact of overlay.
We demonstrate our methodology using TCAD and circuit simulations. We show that overlay impact may not
be negligible, and pessimism reduction techniques should utilize suggested analysis and optimization methods.
Self-aligned double patterning (SADP) lithography is a novel lithography technology that has the intrinsic
capability to reduce the overlay in the double patterning lithography (DPL). Although SADP is the critical
technology to solve the lithography difficulties in sub-32nm 2D design, the questions - how to decompose a
layout with reasonable overlay and how to perform a decomposability check - are still two open problems
with no published work. In this paper, by formulating the problem into a SAT formation, we can answer the
above two questions optimally. This is the first published paper with detailed algorithm to perform the SADP
decomposition. In a layout, we can efficiently check whether a layout is decomposable. For a decomposable layout,
our algorithm guarantees to find a decomposition solution with reasonable overlay reduction requirement. With
little changes on the clauses in the SAT formula, we can address the decomposition problem for both the positive
tone process and the negative tone process. Experimental results validate our method, and decomposition results
for Nangate Open Cell Library and larger test cases are also provided with competitive run times.
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