KEYWORDS: Network on a chip, Multimedia, Telecommunications, Networks, Video processing, System on a chip, Process modeling, Digital signal processing, Modeling, Video
In this paper a topological analysis of different IP distributions focusing on optimal memory placements in regular 2DMeshes
has been performed. As case study, a real MPEG-4 decoder implementation with three memories was chosen. In
order to study the influence of memories in the topology of the network, Arteris NoCexplorer tool was used. The results
inferred from the experiments show how the performance of a multimedia system can be improved if memories are
properly located within a NoC. Furthermore, the present work serves to validate the use of Arteris NoCexplorer for
simulating and modelling complex NoC based designs. In addition, a methodology for determining the best IP
distribution in terms of latency and throughput is presented and its feasibility is demonstrated.
KEYWORDS: Network on a chip, Switching, Network architectures, System on a chip, Clocks, Transistors, Receivers, Telecommunications, Circuit switching, Time division multiplexing
Managing the complexity of designing Systems-on-Chip (SoC) containing billions of transistors requires decoupling
computation from communication. Networks-on-Chip (NoC) have been proposed as a solution for managing this
problem as they meet the reusability, scalability and parallelism requirements of these systems, while coping with power
constraints and clock distribution. In this paper, the implementation of a router's architecture for NoC with both
guaranteed and best-effort services support is described, and some synthesis results are presented. The proposed router
architecture is parameterized on the number of virtual channels, the size of virtual channels, the number of virtual
channels for guaranteed traffic, the relative priority of the guaranteed traffic, and the switching technique.
A novel variable length packet scheduling algorithm focused on real output queue reference architecture is presented in
this paper. The main features of this packet scheduler development are the Quality of Service (QoS) and variable length
packet support. The packet scheduler supports up to eight traffic classes which can be assigned up to two different
priorities. The bandwidth assigned to any traffic class is configurable. The packet scheduler has been described and
simulated in C++ language under uniform and bursty traffic conditions.
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