Roughness has always been a key detractor of the optical losses within the silicon photonics devices. With scaling at 300mm wafer, there is an introduction of new tools such immersion lithography scanner, OPC technique that can help to drive furthermore the optical losses reduction. This study will detail the work done on characterizing multiple steps of the process (Lithography, Etch, Annealing) and using roughness tools such LER (Line Edge Roughness), LWR (Line Width Roughness) and finally PSD (Power Spectral Density) to understand the main detractor of the optical losses at each step. These data will be extracted using SEM imaging from VeritySEM 6i.
Incorporated in relevant design of guiding templates, DSA (Direct Self Assembly) patterning offers a cost-effective manufacturing method to support pattern shrink for advanced technology nodes. The physical characteristics of the BCP moieties and the self-assembly process, pose unique 3D metrology challenges. Pattern fidelity issues of DSA caused by dislocations, forms residual later that can impact pattern fidelity after Etch. Addressing this challenge can assist the R&D groups to monitor material and process quality to meet patterning specifications.
In this paper, we highlight the usage of BSE (Back Scattered Electron) metrology as an innovative approach to characterize the DSA process. Experimental data demonstrate the possibility to characterize the polymer residual layer quality and even assess its thickness for the pattern etch transfer. The quality of the information brought by the BSE imaging make it a must-have to quantify the bottom opening for processed of DSA techniques of pitch multiplication and shrink, from which are not visible with conventional SEM images.
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