In this paper, we demonstrate that the floating capacitor load readout operation has higher readout gain and wider
linearity range than conventional pixel readout operation, and report the reason. The pixel signal readout gain is
determined by the transconductance, the backgate transconductance and the output resistance of the in-pixel driver
transistor and the load resistance. In floating capacitor load readout operation, since there is no current source and the
load is the sample/hold capacitor only, the load resistance approaches infinity. Therefore readout gain is larger than that
of conventional readout operation. And in floating capacitor load readout operation, there is no current source and the
amount of voltage drop is smaller than that of conventional readout operation. Therefore the linearity range is enlarged
for both high and low voltage limits in comparison to the conventional readout operation. The effect of linearity range
enlargement becomes more advantageous when decreasing the power supply voltage for the lower power consumption.
To confirm these effects, we fabricated a prototype chip using 0.18um 1-Poly 3-Metal CMOS process technology with
pinned PD. As a result, we confirmed that floating capacitor load readout operation increases both readout gain and
linearity range.
In this paper, a CMOS image sensor using floating capacitor load readout operation has been discussed. The floating
capacitor load readout operation is used during pixel signals readout. And this operation has two features: 1. in-pixel
driver transistor drives load capacitor without current sources, 2. parasitic capacitor of pixel output vertical signal line is
used as a sample/hold capacitor. This operation produces three advantages: a smaller chip size, a lower power
consumption, and a lower output noise than conventional CMOS image sensors. The prototype CMOS image sensor has
been produced using 0.18 μm 1-Poly 3-Metal CMOS process technology with pinned photodiodes. The chip size is 2.5
mmH x 2.5 mmV, the pixel size is 4.5 μmH x 4.5 μmV, and the number of pixels is 400H x 300V. This image sensor
consists of only a pixel array, vertical and horizontal shift registers, column source followers of which height is as low as
that of some pixels and output buffers. The size of peripheral circuit is reduced by 90.2 % of a conventional CMOS
image sensor. The power consumption in pixel array is reduced by 96.9 %. Even if the power consumption of column
source follower is included, it reduced by 39.0 %. With an introduction of buried channel transistors as in-pixel driver
transistors, the dark random noise of pixels of the floating capacitor load readout operation CMOS image sensor is 168
μVrms. The noise of conventional image sensor is 466 μVrms; therefore, reduction of 63.8 % of noise was achieved.
KEYWORDS: Analog electronics, Amplifiers, Interference (communication), CMOS sensors, Vacuum fluorescent displays, Cadmium sulfide, Voltage controlled current source, CMOS technology, Power supplies, Signal to noise ratio
This paper presents a new analog readout architecture for low-noise CMOS image sensors. A proposed forward noisecanceling
circuitry has been developed in our readout architecture to provide a sharper noise-filtering. The new readout
architecture consists of a column high-gain amplifier with correlated-double-sampling (CDS), a column forward noisecanceling
circuitry, and column sample-and-hold circuits. Through the high-gain amplifier together with the forward
noise-canceling circuitry, this readout architecture effectively reduces random noise of in-pixel source follower and
column amplifier as well as temporal line noise from power supplies and pulse lines. A prototype 400(H) x 250(V)
CMOS image sensor using the new readout architecture has been fabricated in a 0.18 μm 1-Poly 3-Metal CMOS
technology with pinned-photodiode. Both the pixel pitch and the column circuit pitch are 4.5 μm. The input-referred
noise of the new readout architecture is 37 μVrms, which has been reduced by 23 % compared to that of the conventional
readout architecture. The input-referred noise of the pixel with new readout architecture is 72 μVrms, which has been
reduced by 24 % compared to that of the pixel with conventional readout architecture.
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