The ever-increasing energy consumption of Data Centers (DC), along with the significant waste of resources that is observed in traditional DCs, have forced DC operators to invest in solutions that will considerably improve energy efficiency. In this context, Rack- and board-scale resource disaggregation is under heavy research, as a groundbreaking innovation that could amortize the energy and cost impact caused by the vast diversity in resource demand of emerging DC workloads. However disaggregation, by breaking apart the critical CPU-to-memory path, introduces a challenging set of requirements in the underlying network infrastructure, that has to support low-latency and high-throughput communication for a high number of nodes.
In this paper we present our recent work on optical interconnects towards enabling resource disaggregation both on Rack-level as well as on board-level. To this end, we have demonstrated the Hipoλaos architecture that can efficiently integrate Spanke-based switching with AWGR-based wavelength routing and optical feedforward buffering into highport switch layouts. The proof-of-concept Hipoλaos prototype, based on the 1024-port layout, provide latency performance of 456ns, while system level evaluations reveal sub-μs latency performance for a variety of synthetic traffic profiles. Moving towards high-capacity board-level interconnects, we present the latest achievements realized within the context of H2020-STREAMS project, where single-mode optical PCBs hosting Si-based routing modules and mid-board optics are exploited towards a massive any-to-any, buffer-less, collision-less and extremely low latency routing platform with 25.6Tb/s throughput. Finally, we combine the Hipolaos and STREAMS architectures in a dual-layer switching scheme and evaluate its performance via system-level simulations.
The rapid increase of bandwidth requirements across the entire hierarchy of Data Center (DC) networks, ranging from chip-to-chip, board-to-board up to rack-to-rack communications, puts strenuous requirements in the underlying network infrastructure that has to offer high-bandwidth and low-latency interconnection under a low-energy and low-cost envelope. Arrayed Waveguide Grating Router (AWGR)-based optical interconnections have emerged as a powerful architectural framework that can overcome the currently deployed electrical interconnect bottlenecks leveraging the wavelength division multiplexing (WDM) and the cyclic routing properties of AWGRs to offer one-hop, all-to-all communication when employed as N×N routers. However, the majority of previous silicon (Si)-based integrated AWGR demonstrations has either targeted C-band operation, despite the dominance of the O-band spectral region in the DC interconnection domain, or offered coarse-WDM (CWDM) functionality and, as such, were limited in terms of AWGR port count. In this article, we present for the first time to our knowledge, a Dense-WDM (DWDM) 16×16 Si-photonic cyclic-frequency AWGR device targeting O-band routing applications. The fabricated AWGR device features a channel spacing of 1.063 nm (189 GHz), a free spectral range of 17.8 nm (3.15 THz) and a 3-dB bandwidth of 0.655 nm (116 GHz). Its proper cyclic frequency operation was experimentally verified for all 16 channels with channel peak insertion loss values in the range of 3.9 dB to 8.37 dB, yielding a channel loss non-uniformity of 4.47 dB. Its compact footprint of 0.27×0.71 mm2 and low crosstalk of 21.65 dB highlight its potential for employment in future AWGR-based interconnection schemes.
Programmable switching nodes supporting Software-Defined Networking (SDN) over optical interconnecting technologies arise as a key enabling technology for future disaggregated Data Center (DC) environments. The SDNenabling roadmap of intra-DC optical solutions is already a reality for rack-to-rack interconnects, with recent research reporting on interesting applications of programmable silicon photonic switching fabrics addressing board-to-board and even on-board applications. In this perspective, simplified information addressing schemes like Bloom filter (BF)-based labels emerge as a highly promising solution for ensuring rapid switch reconfiguration, following quickly the changes enforced in network size, network topology or even in content location. The benefits of BF-based forwarding have been so far successfully demonstrated in the Information-Centric Network (ICN) paradigm, while theoretical studies have also revealed the energy consumption and speed advantages when applied in DCs. In this paper we present for the first time a programmable 4x4 Silicon Photonic switch that supports SDN through the use of BF-labeled router ports. Our scheme significantly simplifies packet forwarding as it negates the need for large forwarding tables, allowing for its remote control through modifications in the assigned BF labels. We demonstrate 1x4 switch operation controlling the Si-Pho switch by a Stratix V FPGA module, which is responsible for processing the packet ID and correlating its destination with the appropriate BF-labeled outgoing port. DAC- and amplifier-less control of the carrier-injection Si-Pho switches is demonstrated, revealing successful switching of 10Gb/s data packets with BF-based forwarding information changes taking place at a time-scale that equals the duration of four consecutive packets.
As data centers constantly expand, electronic switches are facing the challenge of enhanced scalability and the request for increased pin-count and bandwidth. Photonic technology and wavelength division multiplexing have always been a strong alternative for efficient routing and their potential was already proven in the telecoms. CWDM transceivers have emerged in the board-to-board level interconnection, revealing the potential for wavelength-routing to be applied in the datacom and an AWGR-based approach has recently been proposed towards building an optical multi-socket interconnection to offer any-to-any connectivity with high aggregated throughput and reduced power consumption.
Echelle gratings have long been recognized as the multiplexing block exhibiting smallest footprint and robustness in a wide number of applications compared to other alternatives such as the Arrayed Waveguide Grating. Such filtering devices can also perform in a similar way to cyclical AWGR and serve as mid-board routing platforms in multi-socket environments. In this communication, we present such a 3x3 Echelle grating integrated on thick SOI platform with aluminum-coated facets that is shown to perform successful wavelength-routing functionality at 10 Gb/s. The device exhibits a footprint of 60x270 μm2, while the static characterization showed a 3 dB on–chip loss for the best channel. The 3 dB-bandwidth of the channels was 4.5 nm and the free spectral range was 90 nm. The echelle was evaluated in a 2x2 wavelength routing topology, exhibiting a power penalty of below 0.4 dB at 10-9 BER for the C-band. Further experimental evaluations of the platform involve commercially available CWDM datacenter transceivers, towards emulating an optically-interconnected multi-socket environment traffic scenario.
At the dawning of the exaflop era, High Performance Computers are foreseen to exploit integrated all-optical elements, to overcome the speed limitations imposed by electronic counterparts. Drawing from the well-known Memory Wall limitation, imposing a performance gap between processor and memory speeds, research has focused on developing ultra-fast latching devices and all-optical memory elements capable of delivering buffering and switching functionalities at unprecedented bit-rates. Following the master-slave configuration of electronic Flip-Flops, coupled SOA-MZI based switches have been theoretically investigated to exceed 40 Gb/s operation, provided a short coupling waveguide. However, this flip-flop architecture has been only hybridly integrated with silica-on-silicon integration technology exhibiting a total footprint of 45x12 mm2 and intra-Flip-Flop coupling waveguide of 2.5cm, limited at 5 Gb/s operation. Monolithic integration offers the possibility to fabricate multiple active and passive photonic components on a single chip at a close proximity towards, bearing promises for fast all-optical memories. Here, we present for the first time a monolithically integrated all-optical SR Flip-Flop with coupled master-slave SOA-MZI switches. The photonic chip is integrated on a 6x2 mm2 die as a part of a multi-project wafer run using library based components of a generic InP platform, fiber-pigtailed and fully packaged on a temperature controlled ceramic submount module with electrical contacts. The intra Flip-Flop coupling waveguide is 5 mm long, reducing the total footprint by two orders of magnitude. Successful flip flop functionality is evaluated at 10 Gb/s with clear open eye diagram, achieving error free operation with a power penalty of 4dB.
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