For robustness improvement of inline metrology tools, we propose an inline reference metrology system, named verification metrology system (VMS). This system combines inline metrology and nondestructive reference metrology tools. VMS can detect the false alarm error and the nondetectable error caused by measurement robustness decay of inline metrology tools. Grazing-incidence small-angle x-ray scattering (GI-SAXS) was selected as the inline reference metrology tool. GI-SAXS has high robustness capability for under-layer structural changes. VMS with scatterometry and GI-SAXS was evaluated for measurement robustness. The potential to detect metrology system errors was confirmed using VMS. Cost reduction effect of VMS was estimated for the false alarm case. Total cost is obtained as a sum of the false alarm losses and the metrology costs. VMS is effective for total cost reduction with low sampling. Also, it is important that the sampling frequency of reference metrology is optimized based on process qualities.
For robustness improvement of inline metrology tools, we propose inline reference metrology system “Verification Metrology System (VMS)”. This system combines inline metrology tools and non-destructive reference metrology tools. VMS can detect the false alarm error and the not-detectable error caused by measurement robustness decay of inline metrology tools. GI-SAXS was selected as the inline reference metrology tool. GI-SAXS has high robustness capability for under-layer structure changes. VMS with scatterometry and GI-SAXS was evaluated for measurement robustness. The potential to detect metrology system errors was confirmed using VMS. Cost reduction effect of VMS was estimated for the false alarm case. Total cost is obtained as a sum of the false alarm loss and the metrology cost. VMS is effective for total cost reduction with low sampling. And it is important that sampling frequency of reference metrology is optimized based on process qualities.
Operating Characteristic (OC) curves, which are probabilities of lot acceptance as a function of fraction defective p, are
powerful tools for visualizing risks of lot acceptance errors. The authors have used OC curves for the overlay sampling
optimization, and found that there are some differences in probability of acceptance between theoretical calculation and
empirical estimation. In this paper, we derive a theoretical formulation of the probability of acceptance for several simple
cases by decomposing overlay errors, and show that the origin of the differences is the use of stratified sampling in overlay inspection.
In semiconductor manufacturing, process errors are likely to depart from normal distributions. For data violating the
assumption of normality, classical process capability indices (PCIs) may be misleading in terms of the process behavior.
To avoid this, we propose new PCIs with information on the skewness and the kurtosis of a given distribution. Based on
a Monte Carlo simulation with various distributions, the formulae of the proposed PCIs were optimized. Compared with
Johnson transformation or other approaches, our proposed method is simple in calculation. Therefore, it would have greater applicability for data analysis in semiconductor manufacturing.
The optimizing of sampling plans for process control and lot acceptance inspections is emerging as an important
subject concerning the recent lithography process. With proper acceptance variables, one can reduce sample size using inspection by variables rather than inspection by attributes. The inspection by variables is cost-effective and
desirable. However, it is difficult to apply to a non-normal population. Many cases exist where CD distribution
cannot be regarded as normal. If one applies the acceptance sampling inspection with conventional acceptance
variables@in those cases, the inspections become tighter or are reduced, which is contrary to expectations. The
problem of non-normality, which is an essential property of CD distributions, should be treated extensively. We
found that the above problem can be overcome by modifying the conventional acceptance variables through the
inclusion of the 3rd moment. As a result, 50% reduction of sample size can be realized by introducing the lot
acceptance sampling with new variables.
KEYWORDS: Scanning electron microscopy, Scatterometry, Metrology, Critical dimension metrology, Monte Carlo methods, Inspection, Stereolithography, Manufacturing, Time metrology, Optical proximity correction
Measurement characteristics in scatterometry and critical dimension-scanning electron microscopy (CD-SEM) for lot acceptance sampling of inline CD metrology were investigated by using a statistical approach with Monte Carlo simulation. By operation characteristics curve analysis, producer's risk and consumer's risk arising from sampling were clarified. Single use of scatterometry involves a higher risk, such risk being particularly acute in the case of large intrachip CD variation because it is unable to sufficiently monitor intrachip CD variation including local CD error. Substituting scatterometry for conventional SEM metrology is accompanied with risks, resulting in the increase of unnecessary cost. The combined use of scatterometry and SEM metrology in which the sampling plan for SEM is controlled by scatterometry is a promising metrology from the viewpoint of the suppression of risks and cost. This is due to the effect that CD errors existing in the distribution tails are efficiently caught.
To enhance the quality of Advanced Process Control (APC), the optimization of the sampling plan in critical dimension (CD) metrology is studied through empirical considerations concerning the characteristics of errors and a statistical approach. The metric of the optimization is the accuracy of lot mean estimation. Critical dimension errors are classified into static and dynamic errors. A static error is defined as an error that repeats through lots while keeping its tendency, and a dynamic error as an error whose tendency changes by lot. In the basic concept of our sampling plan, sampling positions and size are determined from the static error and dynamic error, respectively. The balance of the sampling number of the wafer, field, and site under the restriction of total sampling size is optimized by a statistical theory.
KEYWORDS: Scatterometry, Critical dimension metrology, Metrology, Scanning electron microscopy, Monte Carlo methods, Inspection, Time metrology, Statistical analysis, Optics manufacturing, Line edge roughness
Measurement characteristics in scatterometry and CD-SEM for lot acceptance sampling of inline critical dimension (CD) metrology were investigated by using a statistical approach with Monte Carlo simulation. By operation characteristics curve analysis, producer's risk and consumer's risk arising from sampling were clarified. Single use of scatterometry involves a higher risk, such risk being particularly acute in the case of large intra-chip CD variation because it is unable to sufficiently monitor intra-chip CD variation including local CD error. Substituting scatterometry for conventional SEM metrology is accompanied with risks, resulting in the increase of unnecessary cost. The combined use of scatterometry and SEM metrology in which the sampling plan for SEM is controlled by scatterometry is a promising metrology from the viewpoint of the suppression of risks and cost. This is due to the effect that CD errors existing in the distribution tails are efficiently caught.
We evaluated the accuracy of the simulation based on mask edge extraction for mask pattern quality assurance. Edge extraction data were obtained from SEM images by use of TOPCON UR-6080 in which high resolution (pixel size of 2nm) and fine pixel SEM image (8000 x 8000 pixels) acquisition is possible. The repeatability of the edge extraction and its impact on wafer image simulation were studied for a normal 1D CD prediction and an edge placement error prediction. The reliability of the simulation was studied by comparing with actual experimental exposure results with an ArF scanner. In the normal 1D CD prediction, we successfully obtained good repeatability and reliability. In 65nm node, we can predict a wafer CD with the accuracy of less than 1 nm using the simulation based on mask edge extraction. In the edge placement error prediction mode, the simulation accuracy is ~5 nm including edge extraction repeatability and the uncertainty of lithography simulation model.
The simulation with edge extraction more accurately predicts the resist pattern at line-end in which the actual mask pattern may be varied from the mask target (CAD) than a conventional simulation in which CAD is used as a mask pattern. This result supports the view that the wafer simulation with edge extraction is useful for mask pattern quality assurance because it can consider actual mask pattern shape.
We investigated the specifications of scanning electron microscope required for the lithography simulation based on the edge data extracted from an actual reticle pattern in the assurance of reticle pattern in which two-dimensional optical proximity correction is applied. Impacts of field of view, positioning error and image distortion on a lithography simulation were studied experimentally. For the reticle pattern assurance in hp90, the field of view of larger than 16 μm squares, the positioning error within +/- 1 μm and the magnification error of less than 0.3% are needed. Under these conditions, wafer image can be predicted with sufficient accuracy by the simulation.
For advanced process control, a sampling plan for critical dimension measurement is optimized through empirical considerations concerning the nature of error and a statistical approach. The metric of the optimization is the accuracy of lot mean estimation. In this work, critical dimension errors are classified into static and dynamic components. The static component is defined as the error which repeats through lots while keeping its tendency, and the dynamic as the error whose tendency changes by lot. In the basic concept of our sampling plan, sampling positions and size are determined from the static and dynamic error, respectively. The balance of sampling number of wafer, field and pattern is obtained under the restriction of total sampling size by a statistical theory with some assumptions. Based on the concept, we could make a sampling plan for 65 nm CMOS lithography.
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