Mr. Takashi Matsuda Profile

Takashi Matsuda

Staff Engineer at Semiconductor Co

SPIE Involvement:

Author

Publications (2)

Proceedings Article | 23 March 2011 Paper

Mask enhancer technology with source mask optimization (SMO) for 2Xnm-node logic layout gate fabrication

Takashi Matsuda, Shigeo Irie, Tadami Shimizu, Takashi Yuito, Yasuko Tabata, Yuuji Nonami, Akio Misaka, Taichi Koizumi, Masaru Sasago

Proceedings Volume 7973, 797316 (2011) https://doi.org/10.1117/12.878727

KEYWORDS: Photomasks, Source mask optimization, Binary data, Halftones, Logic devices, Lithographic illumination, Phase shifts, Resolution enhancement technologies, Logic, Optical proximity correction

Read Abstract +

Proceedings Article | 13 March 2010 Paper

Mask enhancer technology for sub-100nm pitch random logic layout contact hole fabrication

Takashi Yuito, Hiroshi Sakaue, Takashi Matsuda, Tadami Shimizu, Shigeo Irie, Fumio Iwamoto, Akio Misaka, Taichi Koizumi, Masaru Sasago

Proceedings Volume 7640, 76401B (2010) https://doi.org/10.1117/12.848025

KEYWORDS: Photomasks, Printing, Lithography, Image enhancement, Logic, Transmittance, Lab on a chip, Resolution enhancement technologies, Immersion lithography, Phase shifts

Read Abstract +

View contact details

UPDATE YOUR PROFILE

Is this your profile? Update it now.

Sign into your SPIE.org account

Don’t have a profile and want one?

Create an account on SPIE.org

Keywords/Phrases

Search In:

Publication Years