New inverse methods such as model-based SRAF placement, model-based SRAF optimization, and full main + assist
feature ILT are well known to have considerable benefits in finding flexible mask pattern solutions to improve process
window and CD control. These methods have traditionally relied on compact models that are tuned to match resist
measurements at a single z-height or slice. At this slice in the resist, some critical failure modes such as top loss and
scumming are not detected. In this paper, we describe and present results for a methodology to extend ILT’s process
window improvement capabilities, and to co-optimize mask patterns with awareness of the resist profile. These
improvements are proven to reduce the risk of patterning failures at the bottom and top of critical resist features, which a
typical mask correction process would not alleviate. Ideally, mask optimization would use a full rigorous TCAD resist
model to guide the correction at multiple heights in the resist. However, TCAD models are significantly slower than
compact models in simulations and ILT already has high computational requirements. Therefore, we have generated
compact models which are fitted to the TCAD model resist profile data. We show the significant process window
improvements obtained with this new resist 3D aware ILT methodology.
In a 7 nm node (N7), the logic design requires a critical poly pitch of 42 to 45 nm and a metal 1 (M1) pitch of 28 to 32 nm. Such high-pattern density pushes the 193 immersion lithography solution toward its limit and also brings extremely complex patterning scenarios. The N7 M1 layer may require a self-aligned quadruple patterning (SAQP) with a triple litho-etch (LE3) block process. Therefore, the whole patterning process flow requires multiple exposure+etch+deposition processes and each step introduces a particular impact on the pattern profiles and the topography. In this study, we have successfully integrated a simulation tool that enables emulation of the whole patterning flow with realistic process-dependent three-dimensional (3-D) profile and topology. We use this tool to study the patterning process variations of the N7 M1 layer including the overlay control, the critical dimension uniformity budget, and the lithographic process window (PW). The resulting 3-D pattern structure can be used to optimize the process flow, verify design rules, extract parasitics, and most importantly, simulate the electric field, and identify hot spots for dielectric reliability. As an example application, the maximum electric field at M1 tip-to-tip, which is one of the most critical patterning locations, has been simulated and extracted. The approach helps to investigate the impact of process variations on dielectric reliability. We have also assessed the alternative M1 patterning flow with a single exposure block using extreme ultraviolet lithography (EUVL) and analyzed its advantages compared to the LE3 block approach.
Line width roughness (LWR) remains a critical issue when moving towards smaller feature sizes in EUV lithography. At the same time, negative-tone develop (NTD) resist has become a promising process to get wide process margin at narrow trenches and for block mask layers in optical lithography. Here, we present a study on printing behavior of an EUV NTD resist which was exposed at IMEC on the AMSL NXE:3100 EUV tool. In particular, we analyzed the line width roughness, which was found to be pattern dependent. We calibrated a stochastic resist model to the experimental CD and LWR data. The resulting model was used to analyze and understand the pattern dependent LWR behavior. Simulation results for different LWR process window between iso trench, dense line and iso line was verified with measurement results.
In 7mn node (N7), the logic design requires the critical poly pitch (CPP) of 42-45nm and metal 1 (M1) pitch of 28- 32nm. Such high pattern density pushes the 193 immersion lithography solution toward its limit and also brings extremely complex patterning scenarios. The N7 M1 layer may require a self-aligned quadruple patterning (SAQP) with triple litho-etch (LE3) block process. Therefore, the whole patterning process flow requires multiple exposure+etch+deposition processes and each step introduces a particular impact on the pattern profiles and the topography. In this study, we have successfully integrated a simulation tool that enables emulation of the whole patterning flow with realistic process-dependent 3D profile and topology. We use this tool to study the patterning process variations of N7 M1 layer including the overlay control, the critical dimension uniformity (CDU) budget and the lithographic process window (PW). The resulting 3D pattern structure can be used to optimize the process flow, verify design rules, extract parasitics, and most importantly, simulate the electric field and identify hot spots for dielectric reliability. As an example application, we will report extractions of maximum electric field at M1 tipto- tip which is one of the most critical patterning locations and we will demonstrate the potential of this approach for investigating the impact of process variations on dielectric reliability. We will also present simulations of an alternative M1 patterning flow, with a single exposure block using extreme ultraviolet lithography (EUVL) and analyze its advantages compared to the LE3 block approach.
3D Resist profile aware OPC has becoming increasingly important to address hot spots generated at etch processes
due to the mass occurrence of non-ideal resist profile in 28nm technology node and beyond. It is therefore critical to
build compact models capable of 3D simulation for OPC applications. A straightforward and simple approach is to
build individual 2D models at different image depths either based on actual wafer measurement data or virtual
simulation data from rigorous lithography simulators. Individual models at interested heights can be used by
downstream OPC/LRC tools to account for 3D resist profile effects. However, the relevant image depths need be
predetermined due to the discontinuous nature of the methodology itself. Furthermore, the physical commonality
among the individual 2D models may deviate from each other as well during the separate calibration processes. To
overcome the drawbacks, efforts are made in this paper to compute the whole bulk image using Hopkins equation in
one shot. The bulk image is then used to build 3D resist models. This approach also opens the feasibility of
including resist interface effects (for example, top or bottom out-diffusion), which are important to resist profile
formation, into a compact 3D resist model. The interface effects calculations are merged into the bulk image
Hopkins equation. Simulation experiments are conducted to demonstrate that resist profile heavily rely on interface
conditions. Our experimental results show that those interface effects can be accurately simulated with reference to
rigorous simulation results. In modeling reality, such a 3D resist model can be calibrated with data from discrete
image planes but can be used at arbitrary interpolated planes. One obvious advantage of this 3D resist model
approach is that the 3D model is more physically represented by a common set of resist parameters (in contrast to
the individual model approach) for 3D resist profile simulation. A full model calibration test is conducted on a
virtual lithography process. It is demonstrated that 3D resist profile of the process can be precisely captured by this
method. It is shown that the resist model can be carried to a different lithography process with same resist setup but
a different illumination source without model any accuracy degradation. In an additional test, the model is used to
demonstrate the capability of resist 3D profile correction by ILT.
The extension of 193nm immersion lithography to the 14nm node and beyond directly encounters a
significant reduction in image quality. One of the consequences is that the resist profile varies noticeably,
impacting the already limited process window. Resist top-loss, top-rounding, T-top and footing all play
significant roles in the subsequent etch process. Therefore, a reliable rigorous model with the capability to
correctly predict resist 3D (R3D) profiles is acquiring higher importance. In this paper, we will present a
calibrated rigorous model of a negative-tone develop resist. Resist profiles can be well simulated through
focus and dose, and cases that match well to the experimental wafer data are validated. Such a model can
not only provide early investigation of insights into process limitation and optimization, but can also
complement existing OPC models to become R3D-aware in process development.
With constant shrinking of device critical dimensions (CD), the quality of pattern transfer in IC fabrication depends on the etch process and the exposure process fidelities, and the interaction of lithographic and etching processes is no longer negligible. Etch effect correction with accurate models has become an important component in optical proximity correction (OPC) modeling and related applications. It is now commonly accepted that the lithographic and etch effects should be modeled and corrected in a sequential and staged way: a resist (or lithographic) model should be created and used for lithographic effect compensation, and an etch model should be created and used for etch effect compensation. However, there can be various degrees of separation of these two modeling stages. In order to optimally capture the significant variation in the post-development resist patterns and post-etching patterns, it is helpful to integrate these two processes together for the OPC model calibration practice. In this paper, we analyze the integrated simulation approach in OPC modeling where the entire resist model information is made fully accessible in the etch modeling stage to allow the possibility of resist and etch co-optimization, e.g. through adjusting the resist model to optimally fit the etch data. Furthermore, the integrated simulation technique is integrated into a verification flow to simplify the conventional staged flow.
DRAM chip space is mainly determined by the size of the memory cell array patterns which consist of periodic memory cell features and edges of the periodic array. Resolution Enhancement Techniques (RET) are used to optimize the periodic pattern process performance. Computational Lithography such as source mask optimization (SMO) to find the optimal off axis illumination and optical proximity correction (OPC) combined with model based SRAF placement are applied to print patterns on target. For 20nm Memory Cell optimization we see challenges that demand additional tool competence for layout optimization. The first challenge is a memory core pattern of brick-wall type with a k1 of 0.28, so it allows only two spectral beams to interfere. We will show how to analytically derive the only valid geometrically limited source. Another consequence of two-beam interference limitation is a ”super stable” core pattern, with the advantage of high depth of focus (DoF) but also low sensitivity to proximity corrections or changes of contact aspect ratio. This makes an array edge correction very difficult. The edge can be the most critical pattern since it forms the transition from the very stable regime of periodic patterns to non-periodic periphery, so it combines the most critical pitch and highest susceptibility to defocus. Above challenge makes the layout correction to a complex optimization task demanding a layout optimization that finds a solution with optimal process stability taking into account DoF, exposure dose latitude (EL), mask error enhancement factor (MEEF) and mask manufacturability constraints. This can only be achieved by simultaneously considering all criteria while placing and sizing SRAFs and main mask features. The second challenge is the use of a negative tone development (NTD) type resist, which has a strong resist effect and is difficult to characterize experimentally due to negative resist profile taper angles that perturb CD at bottom characterization by scanning electron microscope (SEM) measurements. High resist impact and difficult model data acquisition demand for a simulation model that hat is capable of extrapolating reliably beyond its calibration dataset. We use rigorous simulation models to provide that predictive performance. We have discussed the need of a rigorous mask optimization process for DRAM contact cell layout yielding mask layouts that are optimal in process performance, mask manufacturability and accuracy. In this paper, we have shown the step by step process from analytical illumination source derivation, a NTD and application tailored model calibration to layout optimization such as OPC and SRAF placement. Finally the work has been verified with simulation and experimental results on wafer.
While critical lithographic feature size diminishes, resist profile can vary significantly as image varies. As a consequence, the final etch results are becoming more dependent on 3D resist profile rather than only a simple 2D resist image as an etch mask. Therefore, it has become necessary to build resist profile information into OPC models, which traditionally only contain 2D information in the x-y plane. At the same time, rigorous lithographic simulators are capable of modeling 3D resist profiles on a small chip area. In this work, one approach is investigated to account for 3D resist profile characteristics in full-chip OPC models with the assistance of rigorous simulation. With measurement data collected from experimental wafers, a rigorous resist model is first calibrated and verified. Then individual compact models are built to match the rigorous resist model profile at specified resist heights. The calibrated compact model for bottom resist line width corresponds to a conventional OPC model while resist profile is described by multiple models specified for certain resist heights, with each model being in the form of conventional compact models. In practice, the bottom model along with one or two models at critical heights are usually sufficient to detect sites where etch results become sensitive to resist profile. It has been found that the rigorous resist profile model can be well matched by the suggested compact models. For a quick application demonstration, hot spots of the etch results in the test case have been shown to be successfully captured by the calibrated compact models.
Extreme ultraviolet (EUV) lithography is one of the leading technologies for 16nm and smaller node device patterning.
One patterning issue intrinsic to EUV lithography is the shadowing effect due to oblique illumination at the mask and
mask absorber thickness. This effect can cause CD errors up to a few nanometers, consequently needs to be accounted
for in OPC modeling and compensated accordingly in mask synthesis. Because of the dependence on the reticle field
coordinates, shadowing effect is very different from the traditional optical and resist effects. It poses challenges to
modeling, compensation, and verification that were not encountered in tradition optical lithography mask synthesis.
In this paper, we present a systematic approach for shadowing effect modeling and model-based shadowing
compensation. Edge based shadowing effect calculation with reticle and scan information is presented. Model calibration
and mask synthesis flows are described. Numerical experiments are performed to demonstrate the effectiveness of the
approach.
Double patterning (DP) was investigated for logic layout by using a rigorous three-dimensional (3D) wafer-topography/lithography simulator with water immersion lithography. With increasing complexity of the DP process, the 3D wafer-topography effect of stack structure must be considered, because of its impact to lithography. The main purpose of this paper is to present how to optimize both process and design to ensure overlap and connectivity of split patterns by solving electro-magnetic field distribution in wafer substrate, as well as resist region. A process window was analyzed varying not only focus, dose, and split masking layers, but also considering topography of substrate stack structures, which cause local reflectivity variations. Arbitrary 45 nm logic layout including an L-shaped pattern was analyzed. The process window of the second litho step was analyzed. Due to the reflection from the hard mask (HM, result of the first litho step), the process window was restricted and became smaller. The other option suggests that swapping the first and second litho masks is a better choice, with respect to the impact of wafer topography. The optimization of the stack process condition was analyzed by using the contour plot of reflectivity, as functions of n, k, and thickness of materials inside the bottom anti-reflective coating. The concept of extended normalized image log slope considering local reflectivity variation from wafer process is able to explain the variation of resist sidewall slope and exposure latitude.Therefore, it is useful to analyze connectivity at the stitching point by using a 3D wafer-topography/lithography simulator and to optimize the combination of the DP process and layout stitching design. Furthermore, as a design of an advanced process, litho-develop litho-etch was simulated.
A negative tone development (NTD) process benefits from the superior imaging performance obtained with light field
(LF) masks to print metal and contact layers, resulting in improved process window. In this paper, we introduce an
inverse Mack development model to simulate the NTD process and validate its process advantage. Based on this model,
a NTD resist model calibration has been carried out and the model results are presented. Various NTD application cases
have been studied and the prediction capabilities of simulations are demonstrated: 1) LF+NTD process helps to achieve a
broader pitch range and smaller feature size compared to the traditional dark field (DF) with positive tone development
(PTD) process. NTD brings a significant improvement in exposure latitude (EL) and MEEF for both line-and-space
(L/S) and contact hole (CH) patterns through pitch. 2) The NTD process has been explored for double exposure
lithography with extreme off-axis illumination using L/S patterns with horizontal and vertical orientation, respectively,
which creates dense contact hole arrays down to a 80 nm pitch. 3) Simulation can also be used to explore new NTD
process variances. We have demonstrated the simulations of the NTD model in applications such as printing specific CH
or Metal patterns, a dual-tone development process and a combination of source mask optimization (SMO) and NTD to
print SRAM patterns at smaller sizes.
In this paper, we discuss the accuracy of resist model calibration under various aspects. The study is done based on an
extensive OPC dataset including hundreds of CD values obtained with immersion lithography for the sub-30 nm
node. We address imaging aspects such as the role of Jones matrices, laser bandwidth and mask bias. Besides we focus
on the investigation on metrology effects arising from SEM charging and uncertainty between SEM image and feature
topography. For theses individual contributions we perform a series of resist model calibrations to determine their
importance in terms of relative RMSE (Root Mean Square Error) and it is found that for the sub-30 nm node they all are
not negligible for accurate resist model calibration.
We have calibrated a physical resist model for extreme ultra-violet (EUV) lithography, and discuss model calibration and validation over a larger set of structures. The study is conducted on an extensive data set, collected at imec, for ShinEtsu resist SEVR-59 exposed on the ASML EUV alpha demo tool (ADT). The data set included more than a thousand measured feature widths (critical dimensions or CD) on wafer and mask. We address practical aspects of the calibration, such as the speed of calibration and selection of calibration input. The model is calibrated by simultaneously fitting 12 process windows of features with different mask CD (32, 36, 40 nm), orientation (horizontal, vertical), and pitch (dense, isolated). The smallest feature size at nominal process condition is a 32 nm CD at a dense pitch of 64 nm. Mask CD metrology was used to fit the model versus actually measured mask CD's. Cross-sectional scanning electron microscopy information was included in the calibration, to tune the simulated resist loss and sidewall angle. The achieved calibration root-mean-squared (RMS) error is ∼1.0 nm. We discuss the elements that were essential to obtain a well calibrated model. We discuss the impact of 3-D mask effects on the Bossung tilt. We demonstrate that a correct representation of the flare level during the calibration is key in order to achieve a high CD predictability at various flare levels. Although the model calibration is performed on a limited subset of the measurement data collected on 12 different patterns (one dimensional structure process windows), its accuracy is validated on a large number of patterns used to calibrate models for optical proximity correction―several hundred different feature types, at nominal dose and focus conditions. These were not included in the calibration; validation RMS results as small as 1 nm can be reached. Furthermore, we study the model's extendibility to two-dimensional end of line structures.
This paper presents a novel mask corner rounding (MCR) modeling approach based on Synopsys' Integrated Mask and
Optics (IMO) modeling framework. The point spread functions of single, double, and elliptical Gaussians are applied to
the IMO mask kernels to simulate MCR effects. The simulation results on two dimensional patterns indicate that the
aerial image intensity variation is proportional to the MCR induced effective area variations for single type corners. The
relationship may be reversed when multiple types of corners exist, where the corners close to the maximum intensity
region have a greater influence than others. The CD variations due to MCR can be estimated by the effective area
variation ratio and the image slope around the threshold. The good fitting results on line-end patterns indicate that the
ΔCD is the quadratic function of the Gaussian standard deviations. OPC modeling on 28nm-node contacts shows that
MCR has significant impact on model fitting results and process window controls. By considering the real mask
geometry effects and allowing in-line calibration of model parameters, the IMO simulation framework significantly
improves the OPC model accuracy, and maintains the calibration speed at a good level.
In this paper, we discuss the performance of EUV resist models in terms of predictive accuracy, and we assess the
readiness of the corresponding model calibration methodology. The study is done on an extensive OPC data set collected
at IMEC for the ShinEtsu resist SEVR-59 on the ASML EUV Alpha Demo Tool (ADT), with the data set including
more than thousand CD values. We address practical aspects such as the speed of calibration and selection of calibration
patterns. The model is calibrated on 12 process window data series varying in pattern width (32, 36, 40 nm), orientation
(H, V) and pitch (dense, isolated). The minimum measured feature size at nominal process condition is a 32 nm CD at a
dense pitch of 64 nm. Mask metrology is applied to verify and eventually correct nominal width of the drawn CD. Cross-sectional
SEM information is included in the calibration to tune the simulated resist loss and sidewall angle. The
achieved calibration RMS is ~ 1.0 nm. We show what elements are important to obtain a well calibrated model. We
discuss the impact of 3D mask effects on the Bossung tilt. We demonstrate that a correct representation of the flare level
during the calibration is important to achieve a high predictability at various flare conditions. Although the model
calibration is performed on a limited subset of the measurement data (one dimensional structures only), its accuracy is
validated based on a large number of OPC patterns (at nominal dose and focus conditions) not included in the
calibration; validation RMS results as small as 1 nm can be reached. Furthermore, we study the model's extendibility to
two-dimensional end of line (EOL) structures. Finally, we correlate the experimentally observed fingerprint of the CD uniformity to a model, where EUV tool specific signatures are taken into account.
Ongoing technology node shrinkage requires the lithographic k1 factor to be pushed closer to its theoretical limit. The
application of customized illumination with multi-pole or pixelated sources has become necessary for improving the
process window. For standardized exploitation of this technique it is crucial that the optimum source shape and the
corresponding intensity distributions can be found in a robust and automated way. In this paper we present a pixelated
source optimization procedure and its results. A number of application cases are considered with the following
optimization goals: i) enhancement of the depth of focus, ii) improvement of through-pitch behavior, and iii) error
sensitivity reduction. The optimization procedure is performed with fixed mask patterns, but at multiple locations. To
reduce optical proximity errors, mask biasing is introduced. The optimization results are obtained for the pixelated
source shapes, analyzed and compared with the corresponding results for multi-pole shaped sources. Starting with the
45 nm node mask topography effects as well as light polarization conditions have significant impact on imaging
performance. Therefore including these effects into the optimization procedure has become necessary for advanced
process nodes. To investigate these effects, the advanced topographical mask illumination concept (AToMIC) for
rigorous and fast electromagnetic field simulation under partially coherent illumination is applied. We demonstrate the
impact of mask topography effects on the results of the source optimization procedure by comparison to corresponding
Kirchhoff simulations. The effects of polarized illumination sources are taken into account.
Currently, EUV and double patterning (DP) are competing technologies for the 22nm hp node. The goal of this paper is
to perform a case study and explore resolution limits on a 32nm contact hole array. In order to investigate the resolution
limit for a DP process quantitatively, considering the substrate topography structure is crucial. We applied wafertopography/
lithography simulation to study the relevant effects in detail. To perform a comparative study between ArF
DP and EUV lithography we first analyzed the resolution limit for DP process. We investigated the performance of a
LDLD and a LFLE (litho-freeze-litho-etch) process by decreasing pitch until the resolution limit was reached. The
possible minimum x- pitch (with y-parallel line, first mask) is 85nm, the minimum y-pitch generated for the second litho
step with x-parallel lines is 90nm. This x-y anisotropic phenomenon is caused by the second litho step, where oblique
incident light propagating through space regions contributes to total image. The bulk image distribution is sensitive to
the material in the spacer region, therefore further process optimization is possible by tuning material properties.
Alternatively the fabrication of 32nm size contact holes with EUV lithography was simulated. Pattern shift due to
shadowing, aberrations and flare effects have been considered. A pitch of 64nm (1:1) can be realized at low flare levels,
but corrections for shadowing and flare are essential. Based on this quantification the gap of possible minimum pitch
between DP and EUV are discussed. Furthermore relation between DP topography effect and SMO are discussed.
We report on a comparison between a full-physical resist model that was calibrated to experimental line/space (L/S) critical dimension (CD) data under the flat-mask (also called "thin-mask" or "Kirchhoff") approximation with the model obtained when using a mask 3-D calculation engine (i.e., one that takes into account the mask-topography effects). Both models were tested by evaluating their prediction of the CDs of a large group of 1-D and 2-D structures. We found a clear correlation between the measured-predicted CD difference and the magnitude of the mask 3-D CD effect, and show that the resist model calibrated with a mask 3-D calculation engine clearly offers a better CD predictability for certain types of structures.
We discuss the methodology of physical resist model calibration for a rigorous lithography simulator under various aspects and assess the resulting predictive accuracy. The study is performed on an extensive optical proximity correction (OPC) dataset, which includes several thousands of critical dimensions (CDs) values obtained with immersion lithography for the 45-nm half-pitch technology node. We address practical aspects such as speed of calibration versus size of calibration dataset, and the role of pattern selection for calibration. In particular, we show that a small subset of the dataset is sufficient to provide accurate calibration results. However, the overall predictive power can strongly be enhanced if a few critical patterns are additionally included into the calibration dataset. Also, we demonstrate a significant impact of the illumination source shape (measured versus nominal top hat) on the resulting model quality. Most importantly, it is shown that calibrated resist models based on a 3-D (topographic) mask description perform better than resist models based on a 2-D (Kirchhoff) mask approximation. Also, we show that a resist model calibrated with one-dimensional (lines and spaces) structures only can successfully predict the printing behavior of two-dimensional patterns (end-of-line structures).
EUV exposure tools are the leading contenders for patterning critical layers at the 22nm technology node.
Operating at the wavelength of 13.5nm, with modest projection optics numerical aperture (NA), EUV projectors allow
less stringent image formation conditions. On the other hand, the imaging performance requirements will place high
demands on the mechanical and optical properties of these imaging systems.
A key characteristic of EUV projection optics is the application of a reflective mask, which consists of a reflective
multilayer stack on which the IC layout is represented by the reflectivity discontinuities1. Several mask concepts can
provide such characteristics, such as thick absorbers on top of a reflective multi-layer stack, masks with embedded
absorbers, or absorber-free masks with patterns etched in a reflective multilayer.
This report analyzes imaging performance and tradeoffs of such new mask designs. Various mask types and
geometries are evaluated through imaging simulations. The applied mask models take into account the topographic
nature of the mask structures, as well as the fundamental, vectorial characteristics of the EUV imaging process.
Resulting EUV images are compared in terms of their process stability as well as their sensitivities to the EUV-specific
effects, such as pattern shift and image tilt, driven by the reflective design of the exposure system and the mask
topography.
The simulations of images formed in EUV exposure tools are analyzed from the point of view of the EUV mask
users. The fundamental requirements of EUV mask technologies are discussed. These investigations spotlight the
tradeoffs of each mask concept and could serve as guidelines for EUV mask engineering.
We discuss the methodology of resist model calibration under various aspects and assess the resulting predictive
accuracy. The study is performed on an extensive OPC data set which includes several thousands of CD values obtained
with immersion lithography for the 45 nm technology node. We address practical aspects such as speed of calibration vs.
size of calibration data set and the role of pattern selection for calibration. In particular, we show that a small subset of
the data set is sufficient to provide accurate calibration results. However, the overall predictive power can strongly be
enhanced if a few critical patterns are additionally included into the calibration data set. Besides, we demonstrate a
significant impact of the illumination source shape (measured vs. nominal top hat) on the resulting model quality. Most
importantly, it will be shown that calibrated resist models based on a 3D (topographic) mask description perform better
than resist models based on a 2D (Kirchhoff) mask approximation. Also, we show that a resist model calibrated with
one-dimensional (lines & spaces) structures only can successfully predict the printing behavior of two-dimensional
patterns (end-of-line structures).
In extreme ultraviolet lithography (EUVL) a reflective mask is illuminated obliquely and the illumination is partially coherent. Due to the small NA (0.25) and sigma (0.5) the incident angles do not vary too much throughout the source distribution, but, unlike in the optical case, the topography is rather pronounced. Moreover the multilayer reflectivity varies significantly even for small variations of the incident angle. So as a result the object spectrum will not only be shifted as a function of the source point, but amplitudes and phases will also vary significantly. On the way to more advanced technology nodes, NA needs to increase up to 0.5, and effects induced by partially coherent illumination could be critical and must be appropriately modeled and investigated. In this paper the impact of the real source distribution on EUVL imaging is investigated. For this a rigorous electro-magnetic field solver is used to predict the subtle effects associated with the three-dimensional topography of the mask absorbers. We introduce the advanced topographical mask illumination concept for rigorous and fast simulation of EUVL mask under partially coherent illumination. Rigorous simulations are performed for line and spaces with an outlook to future technology nodes.
Double patterning (DP) was investigated for logic layout by using rigorous 3D wafer-topography/
lithography simulator with water immersion lithography. With increasing complexity of DP process,
3D wafer-topography effect of stack structure must be considered, because of its impact to
lithography.
The main purpose of this paper is to present how to optimize both process and design to ensure
overlap and connectivity of split pattern, by solving electro-magnetic field distribution in wafer
substrate as well as resist region.
Process window was analyzed varying not only focus, dose and split masking layers, but also
considering topography of substrate stack structures, which cause local reflectivity variations.
Arbitrary 45nm logic layout including L-shape pattern was analyzed. Process window of second
Litho step was analyzed. Due to reflection from Hard Mask, HM (the first Litho step) the process
window was restricted and became smaller. The other option, swapping first and second Litho
masks is a better choice with respect to impact of wafer topography.
The optimization of stack process condition was analyzed by using contour plot of reflectivity, as
functions of n, k and thickness of materials inside BARC. The concept of Extended NILS
considering local reflectivity variation from wafer process is able to explain the variation of resist
sidewall slope and Exposure Latitude. Therefore, it is useful to analyze connectivity at stitching
point by using 3D wafer-topography/ lithography simulator and to optimize the combination of DP
process and layout stitching design. Furthermore as design of advanced process, LLE
(Litho-Litho-Etch), with resist freezing was simulated.
Double Patterning (DP) is considered the most viable solution for printing features of the 32nm technology node using
193nm immersion lithography. Independent of the approach of the DP implementation (be it Litho-Etch-Litho-Etch or
Litho-Process-Litho-Etch), the second lithography step is influenced by the underlying topography on the wafer. Given
the tight constraints on the process, an accurate prediction of the impact of the embedded topography on critical features
is inevitable to meet the design requirements of the corresponding device layer. In this paper we use rigorous simulations
of the electro-magnetic field distribution to quantify the effect of wafer topography on the second lithography step. In
particular, we investigate the impact of the topography on CD control and corresponding process windows for typical 1D
patterns. The influence of non-flat BARC, non-flat resist surfaces, hard mask material and process variations in the first
litho step is simulated for dual line as well as dual trench processes. A metric to quantify standing waves in resist is
introduced and used to optimize BARC thickness. Further, we investigate typical 2D clips of decomposed mask layouts
relevant for the 32nm node. The simulation methodology and algorithm performance are presented, in particular with
respect to its distributed computing capabilities.
KEYWORDS: Photomasks, 3D modeling, Optical proximity correction, Data modeling, Process modeling, SRAF, Data processing, Computer simulations, Electromagnetism, Lithography
32 nm half-pitch node processes are rapidly approaching production development, but most tools for this process are
currently in early development. This development state means that significant data sets are not yet readily available for
OPC development. However, several printing effects are thought to become more prominent at the 32 nm half-pitch
node. One of the most significant effects is the three dimensional (3D) mask effect where the mask transmittance and
phase are impacted by the mask topography. For the 32nm node it is essential that this effect is correctly captured by the
OPC model. As wafer data for the 32nm half-pitch is difficult to obtain, the use of rigorous lithography process
simulation has proven to be invaluable in studying this effect. Using rigorous simulation, data for OPC model
development has been generated that allows the specific study of 3D mask effect calibration. This study began with
Kirchhoff based simulations of 32 nm node features which were calibrated into Hopkin's based OPC process models.
Once the standard Kirchhoff effects were working in the OPC model, 3D mask effects were included for the same data
by performing fully rigorous electromagnetic field (EMF) simulations on the mask. New EMF compensation
methodologies were developed to approximate 3D mask effects in a fast OPC process simulation. These methodologies
modify the phase and transmission of features to compensate for 3D mask effects in a fast OPC model. The OPC model
was then refit including the 3D mask effect and found to generate as much as 5 nm differences between the fit Kirchhoff
data and the fit 3D mask data. In addition, the Hopkin's based OPC model with new EMF compensation methodologies
has been able to fit the 3D mask data with an RMSE value of 0.52 nm and a range of 2.76 nm. These data were
compared to 32 nm half pitch node data from IMEC. In addition the data process models were used for OPC correction
with first principles validation to understand the impact of the 3D mask effect on OPC.
EUV lithography is one of the hot candidates for the 22nm node. A well known phenomenon in EUV lithography is the
impact of non-telecentricity and the mask topography on printing performance. Due to oblique illumination of the mask,
layout, the printed features are shifted and biased on the wafer with respect to their target dimension up to several
nanometers. This effect is inherent to EUV imaging systems. In order to maintain CDU, overlay and registration
requirements, these effects need to be compensated for as part of the lithographic manufacturing process. Conventional
compensation techniques, such as OPC compensation, significantly increase the complexity of the litho process.
In this paper we discuss pattern shift, which is induced by mask-side non-telecentricity of the EUV ring field system. In
particular, we show how the mask position relative to the focal plane of the projection system impacts pattern shift. It is
shown that mask focus shift allows for a compensation of pattern shift, independent on angle of incidence, pattern type,
pattern pitch, pattern orientation, and slit position. Thus it is seen that placement error is not an effect related to mask
topography (not a shadowing effect) but arises purely from the mask non-telecentricity.
A geometric interpretation of this effect is given and shown to be consistent with results of rigorous simulations. A
method to simulate the shift of the mask focus position is briefly discussed. The mask focus shift for which the pattern
shift vanishes in the aerial wafer image at best focus is determined using rigorous simulations. The amount of mask focus
shift to compensate for the pattern shift is found to be approximately 136nm. This mask focus shift is then applied to
investigate the through focus and dose behavior of the pattern shift in the resist. It is shown that the pattern shift is a
function of wafer focus position and that this is a result of the image tilt in EUV systems. While the pattern shift is fully
compensated at one wafer focus position, the shift at other positions is very small. The impact of the mask focus position
on process window is investigated.
KEYWORDS: Photomasks, SRAF, Data modeling, 3D modeling, Optical proximity correction, Process modeling, Computer simulations, Data processing, Electromagnetism, Calibration
32 nm half-pitch node processes are rapidly approaching production development, but most tools for this process are
currently in early development. This development state means that significant data sets are not yet readily available for
OPC development. However, several physical mask effects are predicted to become more prominent at the 32 nm half-pitch
node. One of the most significant effects is the three dimensional (3D) mask effects where the mask transmittance
and phase are impacted by the mask topography. Already at larger process nodes this effect impacts imaging
performance, especially when sub-resolution assist features are employed. For the 32nm node it is essential that this
effect is correctly captured by the OPC model. As wafer data for the 32nm half-pitch is difficult to obtain, the use of
rigorous lithography process simulation has proven to be invaluable in studying this effect. Using rigorous simulation,
data for OPC model development has been generated that allows the specific study of 3D mask effect calibration. This
study began with Kirchhoff based simulations of 32 nm node features which were calibrated into Hopkin's based OPC
process models. Once the standard Kirchhoff effects were working in the OPC model, 3D mask effects were included
for the same data by performing fully rigorous electromagnetic field (EMF) simulations on the mask.
Starting with the 45nm node, the minimum feature size on the mask has reached sub-wavelength dimension. In this
regime the electromagnetic field induced in the mask is significantly impacted by the mask topography. These so called
mask topography effects play an important role in the image formation process and need to be compensated for in the
optical proximity correction (OPC) model. Looking ahead to the 32nm process node, mask topography effects will
become even more pronounced. So, including these effects into the OPC model has become a must for advanced process
nodes. Modern OPC engines start to apply electromagnetic field (EMF) compensation techniques to take these effects
into account. Of course, due to the severe run time constrains for OPC models most EMF aware OPC models need to
rely on approximate methods. A reliable OPC verification process needs to include a fully rigorous treatment of the mask
topography effects with taking into account oblique light incidence and polarization of light. In this paper we investigate
the impact of rigorous mask topography simulation on the reliability of OPC verification and determine the influence of
EMF aware OPC models on OPC quality. We use lithography simulations on OPCed layout cells where we apply a fully
rigorous parallelized EMF solver to the mask model. Two different OPC models are used in this study; one based on the
conventional approach and another one using EMF compensation techniques. The results of the rigorous lithography
simulations are used to verify both OPC models. The impact of the EMF simulation on OPC verification quality is
illustrated by direct comparison with the corresponding Kirchhoff simulations for both OPC models.
A detailed defect printability analysis is reported for conditions that are fully representative for the world's first full field
EUV scanner, using 4X reticles, as obtained by simulation. For absorber type defects the historical rule of thumb
underestimates the printability. An opaque defect located in a space within a 40nm lines and space pattern can already
cause more than a 10% change in the space width from 80% of the space width onwards (>32nm at mask scale, >8 nm at
wafer scale) depending on its location. Absorber type clear defects start affecting line width in 40nm lines and spaces
from about twice the size of an opaque defect. Particles simulated as carbon cubes have a similar effect as absorber type
opaque defects provided that they are about 50% larger. Other possible particle materials are investigated as well. Local
carbon deposition, which may originate from SEM inspection, can cause a printing effect already at a thickness of only
2nm. Multilayer or substrate type defects require surface smoothing to less than about 2nm, as to keep the impact of so-called
phase defects under control. Experimental plans for comparison of simulations to exposures on the ASML Alpha
Demo Tool installed at IMEC are included.
Development of extended optical systems using liquid immersion for patterning enables numerical apertures > 1.2
lithography. Hyper numerical aperture (NA) lithography has to deal with extremely oblique incident light, mask
polarization, mask topography effects and large diffraction angle from mask feature with tight pitch. Simulation tools
predicting highly accurate results based on real experimental data are widely used in the industry and for lithography
process development. Predictability of Optical Proximity Correction (OPC) tools is strongly dependent on the amount
of physical effects taken into account. Therefore going below 45nm half pitch the correct description of the real mask
nature including the effects of mask topography, polarization and pellicle apodization is vital to the success of
immersion lithography.
In this paper we investigate the impact of pellicle apodization effects predicted by simulations for OPC. Significant
pellicle apodization induced CD differences including 1D and 2D OPC structures will be presented. The key emphasis
of this paper is to highlight the criticality of an integrated OPC solution including mask polarization, mask topography
and pellicle apodization effects for enabling immersion lithography moving beyond 45nm and 32nm nodes.
To meet the imaging resolution requirements, driven by the evolution of IC design rules, leading-edge
scanners incorporate projection lenses with hyper-NAs. Moreover, immersion scanners are being
introduced into IC manufacture. Both dry and immersion tools explore the lens design regimes of
unprecedented complexity.
The need to predict, to analyze and to control the IC pattern CDs is met by various photolithography
simulators. The continuing demand for simulation accuracy is reflected by the requirement to quantify
the scanner projection lens fingerprints, i.e. projection lens infinitesimal excursions from the ideal
performance. The scanner engineering community has been relying on photolithography simulators to
analyze the impact of the projection lens fingerprints on the imaging characteristics.
However small, these excursions are always present in the projection tools and they control important
imaging characteristics such as overlay, CD uniformity, across-field exposure latitude, to name but a
few. Customarily, phase front aberrations and lens pupil apodization signatures have been used to
predict the scanners imaging responses. Of course, the need to design, to manufacture and to deploy
scanners of ever improving quality resulted in dramatic reductions of these non-ideal imaging
excursions.
The evolution of IC designs and imaging tools complexity escalate the requirements for imaging
simulation accuracy. Simultaneously, predicting scanner imaging response has become a key mission in
the Deign For Manufacture arena. In view of these developments, it necessary to pose a question if the
conventional equipment engineering and imaging simulation methodologies predict scanner imaging
responses with the accuracy required by the IC design rules. Differently put, the question is: what is
necessary to provide simulation accuracy required by the current IC design rules? This report attempts
to address these questions.
One of the hot topics in the Extreme Ultra-Violet (EUV) mask fabrication process is the requirement to produce multilayer blanks without any printing defects. As the potential of experimental studies is still limited, a predictive simulation of EUV lithography is an important step on the way to meet this requirement. The simulator tool SOLID-EUV is extended to deal with defective multilayers. The simulation is divided into two regions, the finite-difference timendomain (FDTD) method for the absorber part and the simulation of the multilayer reflectivity by the Fresnel-method. To take the defects into account the multilayer is divided into segments, which include the defect and the reflectivity is calculated for each segment. For calculating the multilayer stack for each segment the defects are assumed to be Gaussian shaped. For the complete computation of the reflected light from the EUV mask a coupling of the two methods is realized. This paper presents case studies using the lithography simulator tool SOLID-EUV with the new defective multilayer simulation part, to analyze the printability of defects. The impact of the defect size, horizontal and vertical defect position within the multilayer, and the influence of the layer deposition process is analyzed. The most influential defect parameters are identified. One defect with an influence which tends to be printed is taken and combined with typical mask structures, such as isolated lines, lines and spaces and contact holes. The process windows of the mask structures for various defect positions are analyzed. These simulations can be used to develop strategies to handle such defects.
Standard simulations of optical projection systems for lithography with scalar or vector methods of Fourier optics make the assumption that the wafer stack consists of homogeneous layers. We introduce a general scheme for the rigorous electromagnetic field (EMF) simulation of lithographic exposures over non-planar wafers. Rigorous EMF simulations are performed with the finite-difference time-domain (FDTD) method. The described method is used to simulate several typical scenarios for lithographic exposures over non-planar wafers. This includes the exposure of resist lines over a poly-Si line on the wafer with orthogonal orientation, the simulation of “classical” notch problems, and the simulation of lithographic exposures over wafers with defects.
As the opportunities for experimental studies are still limited, a predictive simulation os EUV lithography is very important for a better understanding of the technology. One of the most critical issues in modeling of EUV lithography is the description of the mask. Typical absorber heights in the range between 80 and 100nm are more than 5 times larger than the wavelength of the used EUV radiation. Therefore, it is virtually impossible to perform parameter studies for 3D EUV masks, such as arrays of contacts or posts, with nowadays standard computers by straightforward application of finite-difference time-domain (FDTD) algorithms, which are used for the rigorous electromagnetic field simulatin of optical masks. This paper discusses the application of field decompsition techniques for an efficient simulation of 3D EUV-masks with FDTD algorithms. Comparisons with full 3D simulations are used to evaluate the accuracy and the performance of the proposed approach. The application of the new QUASI 3D rigorous electromagnetic field simulation for EUV masks reduces memory requirements and computing time by a factor of at least 100. The implemented simulation appraohc is applied for a first exploration of mask induced imaging artifacts such as placement errors, telecentricity errors, Bossung asymmetries, and focus shifts for 3D EUV masks.
Rigorous modeling of diffraction from the mask is one of the most critical points in the extension of lithography simulation from its traditional spectral range between 150 and 500 nm into the area of extreme ultraviolet (EUV) between 10 and 15 nm. A typical EUV mask is made of a reflective multilayer (Mo/Si or Mo/Be for example) deposited on a substrate. Above the multilayer, a buffer layer acts as an etch stopper, and an absorber is used for the mask pattern. If we limit our scope to layers without defect, most of the mask parts can actually be described by analytical methods such as transfer matrices. Therefore we decided to split the mask into two parts : the first part includes the absorber and the buffer layer and it will be studied using a finite-difference time-domain (FDTD) algorithm, the second part includes the reflective multilayer and the substrate and it will be simply described by transfer matrices.
The applicability and accuracy of newly developed analytical models for resist process effects are investigated. These models combine a stationary level set formulation with a lumped parameter model. They allow to propagate the 3D photoresist profile given the 3D aerial image distribution. The first model, based on the vertical propagation algorithm (VPM), takes into account the 2D intensity distribution inside the resist, including the absorption. The second model incorporates the scaled defocus algorithm (SCDF), which describes the 3D intensity of the resist, taking into account the defocus values. In this paper we investigate the applicability for any geometry, for process window determination and the accuracy by taking reference to the fully fledged simulator SOLID-C. The suggested methods allow to calculate 3D resist profile in a fast way thereby enabling the prediction of large areas.
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