The qubit count of superconducting transmon-based quantum processors is steadily increasing. Some processors are already beyond the 100-qubit scale. In order to keep the development cadence of those quantum processors high, the test time per qubit needs to be strongly reduced from days to hours. Here we present a test time study based on extracting a single-qubit fidelity using a randomized benchmarking protocol. We show that more than a dozen other tune-up steps are required before a randomized benchmarking protocol can be executed on a qubit. En bloc, such a structured workflow leads to a test-time of about 20 mins per qubit. By extrapolating, we find that testing single-qubit fidelities on a hecto-qubit scale quantum chip using the randomized benchmarking protocol would take about 2.5 days. Executing the test protocol is furthermore embedded in a total test cycle that takes into account that a chip needs to be inserted, tested, and retrieved from the system, consisting of a cooldown to 20 mK base temperature and afterwards a warmup to ambient conditions. The whole process of chip testing, starting with insertion and ending with the retrieval of the quantum processor under test is estimated to take about a week. Considering the current state of technology, such a cadence in chip testing can be considered high throughput.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.