IBM Research recently announced that 2nm node Nanosheet Technology is able to deliver superior density, power and performance compared to today’s 7nm FinFET technology in mass production. To enable 2nm node Nanosheet Technology, advanced patterning solutions are required. Dimensional compression drives the need for advanced patterning solutions including wider use of extreme ultraviolet (EUV) lithography. This also creates higher in feature aspect ratios, which in turn creates additional challenges during plasma etch. As aspect ratios continue to increase, difficulty with in-feature ion, radical, and volatile species transport during plasma etch presents an exceptional challenge. Dimensional scaling and wider use of EUV increases the need for further reduction of critical dimension (CD) variability, including line edge and line width roughness. The introduction of 3-dimensional gate all around nanosheet architecture has introduced an additional unique set of patterning challenges to address for coming technology nodes. When combined with dimensional scaling there is a clear need for novel advanced patterning process solutions to enable future nodes. In this presentation a variety of these challenges and the impact they will have on device and node scaling will be introduced and reviewed.
Gate all around stacked nanosheet FET’s have emerged as the next technology to FinFET’s for beyond 7-nm scaling. With EUV technology integrated into manufacturing at 7nm, there is great interest to enable EUV direct print patterning for nanosheet technology in the FEOL. While sheet and gate pitches expected for the beyond 7nm node fall within the EUV direct print regime (>40nm), it is unclear if direct print solutions can meet device performance requirements at technology critical sheet widths and gate lengths. Here, we demonstrate electrical performance of nanosheet FET’s with 20 – 80 nm wide sheets with 40-150 nm pitch gates patterned with single expose EUV. We compare results against a benchmark double patterning process towards meeting variability, device and critical dimension targets. We also explore the limits of process and material knobs - resists, illuminations and etch chemistries with the specific goal of reducing LER/LWR and towards shrink for further scaling. Our results demonstrate crossover points between direct print EUV and double patterning processes for nanosheet technology and identify relevant design guidelines and focus areas to successfully enable EUV for the FEOL in nanosheets.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.