In microelectronic device manufacturing, photosensitive organic insulators (POIs) are widely used during passivation steps to protect and preserve the chips from damage due to subsequent processes and from the external environment. To ensure high performance and to maintain chip quality, a well-controlled POI lithography process and corresponding defectivity monitoring are needed. In this work, we present an automated method developed by STMicroelectronics and KLA for POI defectivity and process control employing a KLA 8 Series inspection system with illumination in the visible range. The highly sensitive macro inspection tool with dedicated analysis approaches and solutions successfully enabled the detection of the principal defects of interest, the identification of defectivity root causes through automatic classification and review, and the evaluation of the layer thickness and uniformity through reflected intensity heatmaps. For several months, this protocol has been applied to the production environment, proving to be effective in detecting even small deviations from the standard process. Here, we present some promising results obtained with this strategy, highlighting the benefits in terms of rework reduction and improved equipment management.
Photolithography masks require a periodical inspection and cleaning. The visual inspection is often paired with a mask air blowing to remove eye visible particles. If these steps are run manually they are really critical for mask integrity in terms of contaminations, scratches, fingerprints, pellicle damage... All these potential issues arise during the mask certification process causing mask repelliculization, and, in the worst case, mask scrap with drawbacks linked to production aspects: quality (repetitive defects), cost (mask repels/remake), production lots on hold, non-linear production WIP and non-respect of production commitments. AG8-AGM photolithography engineering team in collaboration with “Gusmini attrezzature industriali” developed a tool called “CK-MASK” able to handle 6” masks and to reduce the risks connected to masks inspection and blowing.
The laser bandwidth and the wavelength stability are among the important factors contributing to the CD Uniformity
budget for a 45 nm and 32nm technology node NV Memory. Longitudinal chromatic aberrations are also minimized by
lens designers to reduce the contrast loss among different patterns. In this work, the residual effect of laser bandwidth
and wavelength stability are investigated and quantified for a critical DOF layer. Besides the typical CD implications we
evaluate the "image placement error" (IPE) affecting specific asymmetric patterns in the device layout. We show that
the IPE of asymmetric device patterns can be sensitive to laser bandwidth, potentially resulting in nanometer-level errors
in overlay. These effects are compared to the relative impact of other parameters that define the contrast of the
lithography image for the 45nm node. We extend the discussion of the contributions to IPE and their relative importance
in the 32 nm double-patterning overlay budget.
CD uniformity budget for a 45-nm NV memory device requires the analysis and compensation of each single contributor
factor. A dedicated simulation tool "CDU Predictor" helps to quantify the impact of main scanner and process factors
for a comprehensive study of the CD Uniformity for an ideal flat wafer. However this analysis could under estimate the
real CD distribution on a real production wafer if artefacts induced by thin-film effects and underling device topography
significantly increase the contribution of the optical leveling-device to the total focus-error and hence spread the CD
distribution for processes with low DOF. Such artefacts can be eliminated by application of an offset-map obtained by
probing the mechanical top-surface of the resist-stack with an AirGauge (AirGaugeImprovedLEvelling, AGILE). The
systematic variation of CD across the wafer, no matter whether due to fingerprints of the reticle, the device-topography,
the track-process or the exposure-tool, can be mapped into dose-corrections for compensation (DoseMapper). We discuss
an experimental case with a combination of both tools for an effective CD Uniformity optimization.
Aggressive pitch requirements for line/space pattern devices require the usage of extreme off-axis illumination schemes
to enhance the resolution of the exposure tools. These illumination schemes stress the quality of the optics because of the
anisotropy of the optical paths through the lens. Moreover, the marginalities on the patterning are dramatically enhanced
if two or more illumination modes are requested in the lithography process.
The effects on overlay between double exposure layers exposed with different illumination settings, with one being an
extreme illumination setting, will be discussed and two approaches will be addressed to compensate the resulting overlay
fingerprint.
The first approach optimizes the lens setup by means of a dedicated scanner option to minimize the lens effects on
overlay and reduce the distortion for each layer: in this case the simulation time and the impact on other imaging
parameters will be carefully evaluated.
The second methodology corrects the induced misalignment by a high order modelling compensation. This approach
requests the insertion of a suitable set of overlay measurement targets into the product frame to appropriately fit the
distortion matching of the two layers.
The merits of hyper NA imaging using 193nm exposure wavelength with water immersion for 45nm is clear. Scanner
focus and dose control is always improving to allow small DOF manufacturing in immersion lithography. However,
other process parameters can affect focus and dose control and a real-time monitor capability to detect local focus and
exposure conditions on production wafers is required. In this paper we evaluated a focus-exposure monitor technique
based on Spectroscopic Critical Dimension (SCD) metrology following the promising results obtained by Kelvin Hung
[1] et al. The key attributes of this technique are the implementation on standard production wafers, the high sensitivity
to pattern profile modifications and the unique capability of spectroscopic ellipsometry to provide all the information
needed to decouple the effects on pattern formation coming from process variations of Advanced Patterning Films (APF)
[2], largely adopted for 65/45nm patterning, from coating and, finally, from the pure scanner imaging contributors like
focus and exposure. We will present the characterization of this technique for 2 critical layers: active and contacts of a
non-volatile memory device, 45nm technology.
Double patterning is the best technique which allows 193nm immersion lithography to anticipate the 32 nm node, before
EUV lithography. The final device pattern is formed by two independent patterning steps where the dense pitch is
doubled. This allows printing each patterning step with higher k1 imaging factor.
In this paper we present the overlay and CD budget applied to a double patterning (DP) technique for the definition of a
32nm technology node device, using an immersion scanner tool. A balance among different factors which affects the
final CD of the device is necessary to optimize the imaging and the alignment performances of the exposure tool. A
preliminary activity is also necessary to choose the most suitable mask splitting strategy. Adopting a single mask, which
is exposed twice with the appropriate shift - the final pitch - , makes the overlay between the two exposures less critical
than splitting the complementary layouts on two different masks. Finally, the CD uniformity of the pooled distributions
from the two exposures is evaluated in order to define the requested tool performances in terms of overlay, CD control
and metrology.
KEYWORDS: Overlay metrology, Metrology, Image segmentation, Front end of line, Semiconducting wafers, Chemical mechanical planarization, Metals, Lithography, Scanning electron microscopy, Scanners
Accurate and precise overlay metrology is a critical requirement in order to achieve high product yield in microelectronic manufacturing. Meeting the tighter overlay measurement error requirements for 90nm technology and beyond is a dramatic challenge for optical metrology techniques using only conventional overlay marks like Bar in Bar (BiB) or Frame in Frames (FiF). New deficiencies, affecting traditional overlay marks, become evident as microlithography processes are developed for each new design rule node. The most serious problems are total measurement uncertainty, CMP process robustness, and device correlation. In this paper we will review the superior performances of grating-based AIM marks to provide a complete solution to control lithography overlay errors for new generation devices. Examples of successful application of AIM technology to FEOL and Cu-BEOL process steps of advanced non volatile memory devices manufacturing are illustrated. An additional advantage of the adoption of AIM marks is that the significant reduction of target noise versus conventional marks revealed systematic differences within the lithography cluster which were previously obscure offering a new tool to optimize litho cells. In this paper we demonstrated that AIM target architecture enables high performance metrology with design rule segmented targets - a prerequisite to have overlay marks fully compatible with design rule sensitive process steps.
To meet lithographic requirements for the 100 nm generation, the influence of laser spectrum bandwidth, illuminator miscalibrations, and lens aberrations on printing of specific patterns by specific customized illuminations has to be investigated. The contribution to critical dimension (CD) dispersion and pattern shift due to lens aberrations of an exposure tool has become an important issue in the production of semiconductor devices. Current 90nm NVM design introduces critical points from the imaging point of view in many layers such as active, poly, contacts and first metallization. The selection of strong off axis illumination shapes and phase shift masks to enhance lithographic resolution and improve process window of such a critical layers may result in a huge impact of lens aberrations. Lens aberrations have a specific impact on the defined layout of the lithographic layer to be printed. An effect similar to the impact of lens aberration can also be induced by illuminator miscalibration and can be enhanced depending on the characteristics of the laser spectrum. The goal of this work is to analyse, for a critical pattern, the contribution to CD dispersion and distortion arising from combined effects of illuminator miscalibration and lens aberrations, depending on laser spectrum characteristics. For this purpose the real pupil shapes through the exposure field and the lens aberrations have been characterized by Litel Instruments HA-SMI and HA-ISI source and aberrations measuring tools to allow reliable optical simulations. Therefore a comparison between simulations and experimental results will be reported for imaging of an NVM critical pattern.
Current 90nm Flash memory design introduces imaging critical points in several devices levels: active, poly, contacts, and first metallization. Among standard Resolution Enhancement Techniques (RET), Off-axis illuminations play a fundamental role, because they are capable of providing better imaging contrast and improved process latitude in low K1 regime with very dense structures. Starting from the simulation study of real device layer geometries, object of this work is to propose a solution in terms of illumination schemes and mask choice (binary or halftone) for each critical layer, considering K1 around 0.35 in ArF lithography. Dedicated off-axis illuminations will be compared to standard illumination modes, underlining the benefits in terms of ultimate resolution, process window and line edge roughness improvement. Experimental data confirmed the predicted gain in process robustness and, as expected, showed great line edge roughness improvement and less marginality to pattern collapse.
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