KEYWORDS: Robotics, Computing systems, Field programmable gate arrays, Robots, Neural networks, System on a chip, Integration, Energy efficiency, Graphics processing units, Application specific integrated circuits
The article discusses a heterogeneous processor based on an open source 64-bit core of the RISC-V architecture, combined with a reconfigurable neural network accelerator. The features of the implementation of a binary matrix neural network on FPGA and its combination with the RISC-V RV64GC core in tasks of cognitive robotics and industrial production are investigated in order to increase safety in the interaction of a robot and a person.
A new image denoising method is proposed in this paper. We are considering an optimization problem with a linear objective function based on two criteria, namely, L2 norm and the first order square difference. This method is a parametric, so by a choice of the parameters we can adapt a proposed criteria of the objective function. The denoising algorithm consists of the following steps: 1) multiple denoising estimates are found on local areas of the image; 2) image edges are determined; 3) parameters of the method are fixed and denoised estimates of the local area are found; 4) local window is moved to the next position (local windows are overlapping) in order to produce the final estimate. A proper choice of parameters of the introduced method is discussed. A comparative analysis of a new denoising method with existed ones is performed on a set of test images.
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