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In this paper, we present two different Optical Proximity Correction (OPC) flows for Si-Photonics patterning. The first flow is regular model based OPC and the second one is based on Inverse Lithography Technology (ILT). The first OPC flow needs first to retarget the input layout while the ILT flow does support skew edges input by tool design and does not need any retargeting step before OPC. We will compare these two flows on various Si- Photonics waveguides from lithography quality, run time and MRC compliance of mask output. We will observe that ILT flow gives the best Edge Placement Error (EPE) and the lowest ripples along the devices. The ILT flow also takes into account the mask rules so that the generated mask is mask rule compliant (MRC). We will also discuss the silicon wafer data where Si-Photonics devices are printed within the two different OPC flows at process window conditions. Finally, for both OPC flows, we will present the total OPC run time which is acceptable in an industrial environment.
Guiding pattern variations impact directly on the placement of the target and one must ensure that it does not interfere with circuit performance. To prevent flaws, design rules are set. In this study, for the first time, an original framework is presented to find a consistent set of design rules for enabling the use of DSA in a production flow using Self Aligned Double Patterning (SADP) for metal line layer printing.
In order to meet electrical requirements, the intersecting area between VIA and metal lines must be sufficient to ensure correct electrical connection. The intersecting area is driven by both VIA placement variability and metal line printing variability. Based on multiple process assumptions for a 10 nm node, the Monte Carlo method is used to set a maximum threshold for VIA placement error.
In addition, to determine a consistent set of design rules, representative test structures have been created and tested with our in-house placement estimator: the topological skeleton of the guiding pattern [1]. Using this technique, structures with deviation above the maximum tolerated threshold are considered as infeasible and the appropriate set of design rules is extracted. In a final step, the design rules are verified with further test structures that are randomly generated using percolation in order to emulate a Placed and Routed (P&R) standard cell block.
This paper presents a method taking into account the overlay variation and the Resist Image simulation across the process window variation to estimate the design sensitivity to overlay. Areas in the design are classified with specific metrics, from the highest to the lowest overlay sensitivity. This classification can be used to evaluate the robustness of a full chip product to process variability or to work with designers during the design library development. The ultimate goal is to evaluate critical structures in different contexts and report the most critical ones.
In this paper, we study layers interacting together, such as Contact/Poly area overlap or Contact/Active distance. ASML-Brion tooling allowed simulating the different resist contours and applying the overlay value to one of the layers. Lithography Manufacturability Check (LMC) detectors are then set to extract the desired values for analysis.
Two different approaches have been investigated. The first one is a systematic overlay where we apply the same overlay everywhere on the design. The second one is using a real overlay map which has been measured and applied to the LMC tools. The data are then post-processed and compared to the design target to create a classification and show the error distribution. Figure:
However, most RET algorithms are based on Manhattan fragmentation (0°, 45° and 90°) which can generate large CD dispersion on masks for photonic designs. Industrial implementation of RET solutions to photonic designs is challenging as most currently available OPC tools are CMOS-oriented. Discrepancy from design to final results induced by RET techniques can lead to lower photonic device performance.
We propose a novel sizing algorithm allowing adjustment of design edge fragments while preserving the topology of the original structures. The results of the algorithm implementation in the rule based sizing, SRAF placement and model based correction will be discussed in this paper. Corrections based on this novel algorithm were applied and characterized on real photonics devices. The obtained results demonstrate the validity of the proposed correction method integrated in Inscale software of Aselta Nanographics.
In this paper we present a hybrid OPC solution based on local ILT usage around hot spots. It is named as Local Printability Enhancement (LPE) flow. First, conventional OPC and SRAF placement is applied on the whole design. Then, we apply LPE solution only on the remaining problematic hot spots of the design. The LPE flow also takes into account the mask rules so that it maintains the mask rule check (MRC) compliance through the borders of the repaired hot spot’s areas. We will demonstrate that the LPE flow enlarges the process window around hot spots and gives better lithography quality than baseline. The simulation results are confirmed on silicon wafer where all the hot spots are printed. We will demonstrate that LPE flow enlarges the depth of focus of the most challenging hot spot by 30nm compared to POR conventional solution. Because the proposed flow applies ILT solution on very local hot spot areas, the total OPC run time remains acceptable from manufacturing side.
In this study, an original approach for DSA full chip mask optical proximity correction based on a skeleton representation of a guiding pattern is proposed. The cost function for an OPC process is based on minimizing the Central Placement Error (CPE), defined as the difference between an ideal skeleton target and a generated skeleton from a guiding contour. The high performance of this approach for DSA OPC full chip correction and its ability to minimize variability error on via placement is demonstrated and reinforced by the comparison with a rigorous model. Finally this Skeleton approach is highlighted as an appropriate tool for Design rules definition.
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