To accommodate the A10 node a further scaling down of the metal line pitch towards MP16 is envisaged. As high NA will be close to its practical limit for direct P16 L/S patterning, low NA self-aligned double patterning (SADP) from P32 towards P16 was explored. First, lithography conditions such as source and stack were optimized by investigating process windows, uLER/uLWR and ebeam defectivity throughout the P32 core patterning process. Then, with the optimized lithography conditions a CDU wafer was subjected to SADP patterning.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.