The influence of the oxide hard breakdown (HBD) path location along the channel in nMOSFETS on the performance and power consumption of a five stages ring oscillator has been evaluated. A simple MOSFET transistor model which takes into account the oxide BD has been used to do the analysis. The results show that in some cases, after oxide BD, the ring oscillator still operates but the circuit could fail due to higher consumption.
A Conductive Atomic Force Microscope (C-AFM) has been used to investigate the nanometer scale electrical properties of Metal-Oxide-Semiconductor (MOS) memory devices with Silicon nanocrystals (Si-nc) embedded in the gate oxide. This study has been possible thanks to the high lateral resolution of the technique, which allows to characterize areas of only few hundreds of nm2 and, therefore, the area that contains a reduced number of Si-nc. The results have demonstrated the capability of the Si-nc to enhance the gate oxide electrical conduction due to trap assisted tunneling. On the other hand, Si-nc can act as trapping centers. The amount of charge stored in Si-nc has been estimated through the change induced in the barrier height measured from the I-V characteristics. The results show that only ~20% of the Si-nc are charged. These nanometer scale results are consistent with those obtained during the macroscopic characterization of the same structures. Therefore, C-AFM has been shown to be a very suitable tool to perform a detailed investigation of the performance of memory devices based on MOS structures with Si-nc at such reduced scale.
This report details the attempts made to realise nanocapacitors for nanoscale MOS based integrated circuits by AFM anodic oxidation, and therefore isolation, of nano-sized squares of poly-silicon, titanium and aluminium on Si/SiO2. Conductive AFM (C-AFM) was used to perform topographical and electrical characterisation. The experiments were performed with contact mode C-AFM, in ambient air, using Pt-Ir, Co-Cr and Ti coated (20nm) n-type silicon cantilevers. Each sample consisted of a 3-5nm thick conductor deposited on 6nm of SiO2, which was thermally grown on Phosphorus doped (1019 cm-3) n-type Si(100) substrates. Standard cleaning and passivation processes were used. Poly-silicon was immediately found to be too rough to oxidise. Initial current-voltage measurements inside of the titanium-oxide squares suggest initial isolation followed by degradation through Fowler-Nordheim tunnelling. Measurement inconsistencies seen suggest charge storage on the surface or tip with the barrier height of the native titanium oxide thought to be responsible. Al has a thicker natural oxide. To overcome this we designed a series of structures consisting of a Ti finger on SiO2, that is connected to a Ti bond pad, allowing direct probing by a semiconductor parameter analyser. AFM anodic oxidation was performed upon these Ti fingers to reduce their in-plane dimensions towards the nanoscale. To confirm the existence of a nanocapacitor topographical and electrical measurements were then done on and around them.
The effect of current limited stresses (CLS) on the breakdown (BD) SiO2 gate oxides has been analyzed at a nanometric scale with a Conductive Atomic Force Microscope (C-AFM). Bare oxide regions have been stresed and broken down using the tip of the C-AFM as the metal electrode of a metal-oxide-semiconductor (MOS) structure. Afterwards, post-BD I-V characteristics and topographical and current images of the affected areas have been obtained to analyze the post-BD conduction, the structural damage induced in the oxide and the BD propagation. The results shwo that BD phenomenon, although triggered at one point, is electrically propagated to neighbor regions. Moreover, the area affected by BD, the structural damage and the post-BD conduction depend on the breakdown hardness. In particular, it is shown that these magnitudes are smaller when the current through the structure is limited during BD transient.
Atomic Force Microscopy (AFM) has been demonstrated to be one of the most powerful tools for nanoelectronic fabrication and characterization. However, AFM grown SiO2 has not been yet used as the gate dielectric, and its electrical behavior remains still unknown. After a topographic characterization, in this paper the conduction modes of AFM grown gate oxide (AFM-GOX) MOS structures are studied from measurements of their current-voltage (IV) characteristics. The results are compared to those obtained for thermally grown SiO2 (T-GOX), which is used as quality reference. Two types of structures have been used to study the conduction through AFM-GOX: a) MOS capacitors with polysilicon deposited gate, for standard electrical characterization and b) MOS structures without deposited gate, because the conductive AFM tip acts as gate terminal, for Conductive-AFM (C-AFM) measurements. Qualitatively, the fabrication process of the poly-Si gated structures consisted of: a field oxidation of the Si wafers, opening of windows in the field oxide to reach the substrate, then AFM oxidation was performed (4nm thick oxide), and as a last step a polysilicon gate was deposited. For the reference structures, AFM gate oxidation process was replaced by thermal oxidation with thickness of 3.5 and 4.5nm. The substrate was n-type Si.
The standard electrical characterization, reveals that the dielectric breakdown of T-GOX happens at higher voltage than for AFM-GOX. Moreover, the current level through AFM GOX at voltages below the breakdown value is several orders of magnitude larger than that measured at same voltages for thermal oxides. These differences could be caused by defects introduced during the AFM oxidation, performed in ambient air. However, a comparison between the IV curves of AFM-GOX and T-GOX measured by C-AFM shows that at a nanometer scale both oxides behave similarly.
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