×We report a computation of the partially coherent imaging with a polarized illumination using an improved SVD
algorithm applied to the stack pupil shift matrix computation method. The case of a polarized source is taken into
account by directly stacking the x-, y- and z-direction stack pupil shift operator. The polarization of the source is
described with a 22 coherency matrix which is decomposed into two independent polarization modes with certain
weights determined by the polarization. For each of the polarization, we compute the stack pupil shift function in each of
the x-, y- and z-direction. For a fast computation the aerial image, the SVD algorithm is applied to each of the polarized
directional kernel. In this way, the total complexity of the SVD computation is reduced. To compute the full mask
image, we compute the sum of convolution of the eigenvectors of each of the kernels and a 2D mask. For a fast decaying
spectrum of the stack pupil shift matrix, we make the truncation of the sum with an estimate of the global precision. In a
test with an annular source, we design a mask pattern. The result in the zero polarization case of our computation agrees
with that of a computation with the Prolith® simulator.
In this paper, we present the Luminescent's ILT approach that can rapidly solve for the optimal photomask design. We
will discuss the latest development of ILT at Luminescent in the areas of sub-resolution assist feature (SRAF) generation
and optimization to improve process window, and mask rule compliance (MRC). Results collected internally and from
customers demonstrate that ILT is not only an R&D tool, but also a tool quickly maturing for production qualification at
advanced technology nodes. By enforcing the proper constraints while optimizing the masks, ILT can improve process
windows while maintaining mask costs at a reasonable level.
In this paper, we present the Luminescent's ILT approach that can rapidly solve for the optimal photomask design. We
will discuss the latest development of ILT at Luminescent in the areas of sub-resolution assist feature (SRAF)
generation, process-window-based ILT and mask rule compliance (MRC). Results collected internally and from
customers demonstrate that ILT is not only an R&D tool, but also a tool quickly maturing for production qualification at
advanced technology nodes. By enforcing the proper constraints while optimizing the masks, ILT can improve process
windows while maintaining mask costs at a reasonable level.
An implementation of inverse lithography technology is studied with special attention to
illustrating and analyzing the placement, accuracy, and efficacy of subresolution assist elements.
One-dimensional placement through pitch is characterized, and 2D capability is demonstrated for
repeated patterns. Differences between the methods of mask preparation afforded by this system
as compared to current practices are described.
Inverse Lithography Technology (ILT) is a rigorous approach to determine the mask shapes that produce the desired on-wafer
results. In this paper, we briefly describe an image (or pixel))-based implementation of ILT in comparison to OPC
technologies, which are usually edge-based. Such implementation is more computationally scalable and avoids laborious
segmentation script-writing, which becomes more complex for newer generations because of complicated proximity
effects. In this paper, we will give an overview of ILT, present some simulation and wafer examples to demonstrate the
benefit of ILT, clarify common myths about ILT, discuss and show examples to illustrate the impact in every step of the
mask making process. Specifically, studies done with several leading mask shops around the world on mask
manufacturability (including data fracturing, writing strategy and writing time, mask inspection), will be shown.
In this paper we describe, from the user's point of view, how Inverse Lithography Technology (ILT) differs from Optical Proximity Correction (OPC). We discuss some specifics of ILT at chip-scale. We show simulation and experimental results from 90nm and 65nm semiconductor nodes, comparing results from ILT-generated masks and OPC-generated masks for real-life layouts, in a production environment. In addition, we discuss issues related to complexity and manufacturability of ILT-generated masks.
Inverse lithography technology (ILT) was studied during process development for four layers from memory semiconductor designs. This paper describes techniques used in each of the layers. So as to demonstrate this technology in a wide range of semiconductor patterns, we show results from all four layers. Polysilicon was chosen to demonstrate the selection of exposure/defocus (ED) points for constraining the inversion. Marking process window boundaries during a mask creation run was demonstrated on a contact hole layer. With a deep trench layer, mask constraints were varied and write times studied. Lastly, wafer SEM images were collected for an active layer to explore image fidelity though focus and CD stability along a line.
This paper presents the results of applying ILT to SMIC's first 65nm tape out. ILT mathematically determines the mask features that produce the desired on-wafer results for best pattern fidelity, largest process window or an desired combination of both. SMIC applied this technology to its first 65nm tape-out to study its performance and benefits for deep sub-wavelength lithography. SMIC selected 3 SRAM designs as the first set of test cases, because SRAM bit-cells contain features which are lithographically challenging. Firstly, three experiments were performed to optimize the illumination and mask design of a pair of layers by optimizing exposure energy, enabling SRAF, and enforcing mask constraints. Secondly, mask manufacturability (including fracturing and writing time) and wafer print performance of ILT was studied. Thirdly, mask patterns generated by both conventional Optical Proximity Correction (OPC) and ILT, both using only their optical models, were placed on the mask side-by-side. The results demonstrated that ILT achieved better CD accuracy and produced significantly larger process window than conventional OPC.
In this paper we present unintuitive patterns generated by inverse lithography technology. We show examples of contact hole masks designed with ILT that enjoy larger process windows than OPC. We also show variations in ILT-generated masks as the pitch of the contact hole array changes. In another example, we show poly masks designed for better process window to be substantially different from poly masks designed for better fidelity at nominal exposure-defocus (ED) condition. The mask with better fidelity has broken lines in comparison to the original layout. In a third example, we show deep trench mask patterns designed with ILT that, at first glance, bear no resemblance to the original layout, yet provide high fidelity in optical images. These patterns, although complex at first sight, can be generated in substantially simpler form with proper constraints without losing the spirit of ILT masks.
As photolithography is pushed to fabricate deep-sub wavelength devices for 90nm, 65nm and smaller technology nodes using available exposure tools (i.e., 248nm, 193nm steppers), photomask capability is becoming extremely critical. For example, PSM masks require more complicated processing; aggressive OPC makes the writing time longer and sometimes unpredictable; and, high MEEF imposes much more stringent demands on mask quality. Therefore, in order for any new lithography technology to be adopted into production, mask manufacturability must be studied thoroughly and carefully. In this paper we will present the mask manufacturability study on mask patterns created using Inverse Lithography Technology (ILT). Unlike conventional OPC methodologies, ILT uses a unique outcome-based technology to mathematically determine the mask features that produce the desired on-wafer results. ILT solves the most critical litho challenges of the deep sub-wavelength era. Potential benefits include: higher yield; expanded litho process windows; superb pattern fidelity at 90, 65 & 45-nm nodes; and reduced time-to-silicon - all without changing the existing lithography infrastructure and design-to-silicon flow. In this study a number of cell structures were selected and used as test patterns. "Luminized patterns" were generated for binary mask and attenuated phase-shift mask. Both conventional OPC patterns and "luminized patterns" were put on a test reticle side by side, and they all have a number of variations in term of correction aggressivity level and mask complexity. Mask manufacturability, including data fracturing, writing time, mask inspection, and metrology were studied. The results demonstrate that, by optimizing the inspection recipe, masks created using ILT technology can be made and qualified using current processes with a reasonable turn-around time.
This paper presents SMIC's first 65nm tape out results, in particularly, using ILT. ILT mathematically determines the mask features that produce the desired on-wafer results with best wafer pattern fidelity, largest process window or both. SMIC applied it to its first 65nm tape-out to study ILT performance and benefits for deep sub-wavelength lithography. SMIC selected 3 SRAM designs as the first test case, because SRAM bit-cells contain features which are challenging lithographically. Mask patterns generated from both conventional OPC and ILT were placed on the mask side-by-side. Mask manufacturability (including fracturing, writing time, inspection, and metrology) and wafer print performance of ILT were studied. The results demonstrated that ILT achieved better CD accuracy, produced substantially larger process window than conventional OPC, and met SMIC's 65nm process window requirements.
In this paper we describe, from the user's point of view, how Inverse Lithography Technology (ILT) differs from Optical Proximity Correction (OPC). We show simulation and experimental results from 90nm and 65nm semiconductor nodes, comparing ILT-generated masks and OPC-generated masks for real-life layouts, in a production environment. In addition, we discuss issues related to complexity and manufacturability of ILT-generated masks.
Among many advanced contact-hole imaging methods, the vortex phase-shift mask had been shown to have excellent image quality by Marc Levenson et al. [1, 2]. Whereas, the double line-space phase shift mask [3] provides the ultimate resolution enhancement. However, both methods are restricted to uniform contact-hole arrays or contact holes on uniform grid requiring double exposures. In this paper, we show, step-by-step, how to convert a random contact-hole layout into a vortex PSM suitable for single exposure or double line-space PSM masks. We have developed a software program to automatically do the contact-hole pairing, phase-shifter creation, phase assignment and conflict resolution. Further, we present image quality evaluations of memory, uniform contact-hole array and basic vortex pairs. Our results indicate our method (general vortex phase-shift mask) enjoys a process window 2 times that of alternating phase-shift method for both memory and uniform contact-hole array. We further show how simple manual OPC can be added to correct image asymmetry issues associated with vortex mask. Finally, we will discuss the challenges remaining for OPC of single exposure vortex PSM for random logic layout.
Vortex phase-shift mask had been shown to have excellent image quality by Marc Levenson et al. [1, 2]. However, its application has been restricted to uniform contact-hole arrays and non-uniform contact holes on uniform grid requiring double exposure technique. In this paper, we show that random contact holes in a real layout can be imaged using vortex phase shift mask, with a single exposure. We use a DRAM contact-hole layout as an example. At minimum half-pitch size of 80nm (k1=0.28) and pitch of 160nm, using 193nm stepper with 0.68 numerical aperture and 0.3 degrees of partial coherence, we are able to achieve 0.4um DOF with 10% exposure latitude. The possibility of using a single exposure and low NA stepper should far outweigh the increased cost of vortex mask for high volume products. In comparison, the corresponding alternating phase-shift mask, however, can only achieve 0.2um DOF at 10% exposure latitude, even with the aid of higher numerical aperture of 0.90 and high degrees of partial coherence of 0.15. For non-uniform contact holes, image asymmetry is an issue. We show OPC-corrected images that are substantially symmetrical. Phase error is always a concern for any phase-shift mask. We show that substantial process windows remain even in the presence of phase errors. Furthermore, we demonstrate that random contact-hole layout can be successfully phase-shifted using vortex phase-shift method. Finally, we shall that the same phase-shift mask design technology for vortex mask can be applied to double line-space phase-shift mask method [3].
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