Proceedings Article | 10 April 2024
Noyeong Chung, Gwangseok Maeng , Insung Kim, Nivea Schuch, Charles Valade, Antoine Legrain, Frederic Robert, Thiago Figueiro, Jeong-Ho Yeo, Noam Oved, Uri Smolyan, You Jin Kim, Michael Shifrin
KEYWORDS: Metrology, Overlay metrology, Scanning electron microscopy, Semiconducting wafers, Critical dimension metrology, Metals, High volume manufacturing, Contour extraction, Computer aided design, Design
Edge Placement Error (EPE) is a construction metric which can be derived from CD (critical dimension), Overlay and LER (Line Edge Roughness) measurements from multiple layers, and is well accepted as a critical metric of patterning control due to the increases of process complexity as the design rule shrinkage of CMOS devices. Historically, these conventional metrics are measured from multiple tools on different patterns and locations; for example – overlay, on an optical tool from scribe-line target at ADI (After Develop Inspection) step, while CD/LER data are measured using a CD-SEM tool on a real device pattern at ADI/ACI (After Clean Inspection) steps. TMU (Total Measurement Uncertainty) increasement, which causes the consistency of EPE analysis, is the major limiting factor with the constructive EPE approach. Hence implementing EPE with the constructive way as in-line monitoring metric is not practical and straightforward way. This limitation on traditional EPE methodology can be overcome through single image-based approach, where EPE is measured directly from the high landing energy see-through image. Another advantage is that in parallel it provides CD, Overlay and local variability measured at once on a real device feature. All-In-One (AIO) means all EPE related metrics (CD, Overlay, LER, EPE metric) are captured with single image, which is inherently delivering TMU of sub nm level. Continuous device scaling requires tighter TMU in patterning process integration and control. Fabrication of complex structures demands extremely precise overlay and critical dimension measurement along the sequential processes which drives to a holistic approach on EPE metrology, which can be enabled by new 3D see-trough measurement where traditionally 2D metrics are given. Thanks to the high-resolution see-through image under high keV e-beam, interlayer 3D-EPE measurements on complex geometries can be precisely captured and analyzed. See-through image at ADI step is enabled with recent developments on higher keV e-beam system. Overlay metrology on real pattern at ADI was demonstrated and shown the overlay NZO (Non-Zero Offset) error decomposition between lithography and other processes. For the ADI EPE analysis, the contour extraction from low contrast image is another key enabler together with design-based metrology. Utilizing ADI and ACI AIO image of high landing energy SEM and the contour metrology, EPE metrics can be measured along the process steps and analyzed through contours to design intent. An illustration of such type of measurements is shown in Figure 1. In this paper, we will first demonstrate EPE analysis using AIO image both ADI and ACI step and, second, show how the potential weak patterns with the consideration of 3D-EPE can be measured and extracted through the combination of the AIO see-through imaging of ADI and ACI and the design-based contour metrology. In the long run, 3D-EPE aware weak patterns needs to be qualified as HVM (High Volume Manufacturing) in-line monitoring EPE metric like the traditional CD and Overlay metrology. These design-based 3D-EPE capability of HVM can be expanded and enhanced with the big data nature in production and the new metrology can be potentially improved with the machine learning based technology.
