Image inpainting is promising but challenging in computer vision tasks; it aims to fill in missing regions of corrupted images with semantically sensible content. By utilizing generative adversarial networks (GAN), state-of-the-art methods have achieved great improvements, but the ordinary GAN generally suffers from difficulties in training and unstable gradients, leading to unsatisfactory inpainting results. Image-level predictive filtering is a widely used restoration method that adaptively predicts the weights of pixels around a target pixel and then linearly combines these pixels to generate the image, but it cannot fill larger missing regions. Thus, we extend image-level predictive filtering to the deep feature level through an encoder–decoder network and embed adaptive channel attention and spatial attention modules in the encoder network. We use Wasserstein GAN instead of normal GAN due to its superior properties and then combine it with image-level predictive filtering and deep feature-level predictive filtering, which ultimately leads to a significant improvement in image inpainting. We validate our method on two public datasets: CelebA-HQ and Places2. Our method demonstrates good performance across four metrics: peak signal-to-noise ratio, L1, structural similarity index measure, and learned perceptual image patch similarity.
Image defogging has important application value in preprocessing technology and computer vision system. Dark channel prior (DCP) is simple and effective in many defogging algorithms, but the time-consuming sorting comparison and a large number of calculation refinement processes limit its real-time processing capabilities. For real-time applications, we proposed a hardware architecture for single-image defogging, which gives full play to hardware parallel processing capability and algorithmic parallelism. First, an average statistical approach is used to estimate atmospheric light. Then, the refined dark channel map is used for transmittance estimation to reduce the blocking effect. The transmittance is linearly corrected to prevent color distortion in outdoor scenes containing sky areas. Finally, a guided filter algorithm is introduced in the transmittance refinement, and its fast mean filter uses an adaptive window to process the image boundary. The hardware implementation of the proposed method uses field programmable gate array device is Zynq-7000. Experimental results show that our design obtains good performance with low-complex hardware implementation and shorter execution time. It only takes 7.43 ms to process a 1280 × 720 image, and the frame rate can reach 135 fps at a clock rate of 125 MHz, which can be used as a real-time hardware accelerator for image processing.
As the increase of circuit density and switching speed, the crosstalk faults may arise in the adjacent signal lines of VLSI circuits, which are the interference effects caused by parasitic inductance and capacitance coupling. The crosstalk delay fault is one of the crosstalk faults, it may create the additional delay in the circuit, thus it may result in the unexpected time sequence and logic function errors. In this paper, a new approach is presented for the testability analysis of crosstalk delay faults, the approach can decide whether there are test vectors for a crosstalk delay fault in a circuit. First of all, several binary decision diagrams of a circuit are constructed. Secondly, the testability analysis of crosstalk delay faults is carried out by performing a lot of operations on these binary decision diagrams. One advantage of the approach in this paper is that the test vectors of crosstalk faults can be generated quickly after the testability analysis has been carried out, therefore the approach is able to cut down the test time in comparison with generating the test vectors directly.
Several types of defects in the LED chips may be caused from the manufacturing environments, these defects can result in the degradations of the parameters and performance. Hence it is very necessary to perform the defect detection of LED chips for effectively enhancing the production quality. In this paper, a new method is presented for the defect inspection of LED chips. The method makes use of both the support vector machine and the image segmentation based on level set to acquire the features of LED chip images and to carry out the inspection. First of all, the support vector machine is used to perform the clustering for the original LED images, the margin of region clustering is used as the initial contour curve. Secondly, the segmentation using level set is implemented for the LED images. The features of LED images are extracted, then the database of features is constructed. Therefore, an automatic inspection system for LED chip is built, the system can recognize the defective LED chips. The experimental results demonstrate that the presented method in this paper is able to detect the defects in the LED chips accurately.
KEYWORDS: Network on a chip, Structural design, Telecommunications, Switches, System on a chip, Networks, Network architectures, Genetics, Genetic algorithms, Data communications
The network-on-chip (NoC) is a scalable and flexible infrastructure for the design of system on chip (SoC). The
performance of data communication in a network-on-chip depends heavily on the topology structure and routing
algorithm. The communication bandwidth requirements of a network-on-chip can be reduced when the irregular
topology structures are designed for specific application systems. In this paper, a new method is presented for designing
the structure of network-on-chip, the method is based on the evolutionary strategies. First of all, the initial topology
structures are produced by the random approach. Secondly, the topology structures are coded as individuals, and the
topology structure corresponding to an individual is strongly connected, that is there is a path between every pair of
nodes. The feasible topology structures can be obtained by applying the operations in the evolutionary strategies to the
population being consisting of individuals. The experimental results demonstrate that the method proposed in this paper
can obtain the feasible topology structure of network-on-chip.
KEYWORDS: Neural networks, Neurons, System on a chip, Telecommunications, Data modeling, Bismuth, Algorithms, Evolutionary algorithms, Genetic algorithms, Particle swarm optimization
In the design procedure of system on chip (SoC), it is needed to make use of hardware-software co-design technique
owing to the great complexity of SoC. One of main steps in hardware-software co-design is how to carry out the
partitioning of a system into hardware and software components. The efficient approaches for hardware-software
partitioning can achieve good system performance, which is superior to the techniques that use software only or use
hardware only. In this paper, a method based on neural networks is presented for the hardware-software partitioning of
system on chip. The discrete Hopfield neural networks corresponding to the problem of hardware-software partitioning is
built, the states of neural neurons are able to represent whether the required components or functionalities are to be
implemented in hardware or software. An algorithm based on the principle of simulated annealing is designed, which can
be used to compute the minimal energy states of neural networks, therefore the optimal partitioning schemes are obtained.
The experimental results show that the hardware-software partitioning method proposed in this paper can obtain the near
optimal partitioning for a lot of example circuits.
Binary decision diagram can be used to give canonical representation to logic functions and manipulate functions by
simple and efficient graph algorithms. In this paper, the generation of test pattern based on binary decision diagrams is
studied for stuck-at faults and crosstalk faults in digital circuits. The binary decision diagrams corresponding to the
normal circuit and faulty circuit are built, respectively. A binary decision diagram is built by the XOR operation of the
two binary decision diagrams, each input assignment that leads to the leaf node labeled 1 is a test vector of the faults.
Besides, the binary decision diagram is very sensitive to the variable ordering, the variable ordering used can have a
significant impact on the number of nodes. A chaotic genetic algorithms is presented in this paper, which is used to find
a variable ordering that minimizes the size of a binary decision diagram to get the test vectors of the faults in digital
circuits in the shortest possible test time. Experimental results obtained with a lot of digital circuits show that all the test
vectors of a fault can be obtained using the method presented in this paper.
The increase in signal switching speed and density of digital circuits leads to the crosstalk faults of interconnection lines,
which may cause undesirable effects and even logic errors in the circuit. A new test method based on the neural network
models of digital circuits is proposed in this paper for the crosstalk faults in digital circuits. The neural network
corresponding to digital circuit is built, and the test vectors of the crosstalk faults are generated by computing the
minimum energy states of neural network. A chaotic evolutionary strategies algorithm is designed to compute the
minimum energy states. The algorithm combines the features of chaotic systems and evolutionary strategies, and takes
full advantages of the stochastic properties and global search ability of the two techniques. Experimental results on a lot
of benchmark circuits show that the approach proposed in this paper can be used to get the test vectors of the crosstalk
faults if the crosstalk faults are testable.e
Test scheduling is an important task for the test of a system on chip, and it determines the assignment of cores to the test
access mechanism such that the overall test time is minimized. A new test scheduling approach based on cultural
algorithms for system on chip is presented in this paper. First of all, the optimization model of test scheduling is given,
the model uses the information such as the bits width of the test access mechanism and the scale of test sets of cores, the
crosstalk fault test sets of core interconnect lines is also discussed. Secondly, a method based on cultural algorithms is
proposed to solve the optimization model of test scheduling. The ant colony algorithm is used in the population space,
and the conventional genetic algorithm is used in the belief space. The feasible solutions of test scheduling are
represented by individuals, a lot of individuals form the populations. The optimal test scheduling scheme is obtained by
the evolution of the populations. Experimental results on a lot of benchmark circuits show that the proposed approach in
this paper can solve the problem of test scheduling effectively.
In the current circuit design technology, due to increasing device density and operation speed, crosstalk effects are
induced between circuit elements. A new method for the detection of crosstalk faults in digital circuits is presented in this
paper, the method is based on both the energy function model of digital circuits and the chaotic ant colony algorithms.
First of all, the energy function models of basic gate circuits are constructed, then the energy function corresponding to a
digital circuit is built. The energy function of a circuit is the summation of all energy functions of the gates in the circuit.
The test vectors of crosstalk delay faults in the circuit are produced by computing the minimal energy states of energy
functions. Secondly, a chaotic ant colony algorithm is designed to compute the minimal energy states. Experimental
results show the method proposed in this paper is able to produce the test vectors of crosstalk delay faults if there are the
test vectors for the faults, therefore the high fault coverage can be obtained by the proposed method.
The integrated circuit (IC) design technology has made the chip density continue to increase. The high performance chips have a high sensitivity to the slightest defects in manufacturing procedure, therefore the defect detection is needed in order to ensure the performances of chip and semiconductor device. For the defects on a wafer, a detection method using image segmentation is presented in this paper. The method performs the segmentation of wafer image by selecting the threshold values. The optimal thresholds are computed by the technique based on cultural algorithm. The designs of population space, the belief space, and communication protocol in the cultural algorithm, are given in detail. An integration of genetic algorithm and simulated annealing is used to produce the new individuals in the population space. The experimental results show that the defect detection method proposed in this paper can obtain the features of defects effectively, the better image about the defect on a wafer can be obtained if the differential chart of the original image and the intact image of wafer is computed in advance.
The image segmentation is often an important step in the analysis of images. In this paper, an image segmentation method based on cultural algorithms is presented. The method performs the image segmentation by selecting the optimal threshold values. The multi-threshold values are used. First of all, an entropy function corresponding to an image is defined. The optimal threshold values are obtained by making the entropy function reach the maximal value. Secondly, an algorithm based on the principle of cultural algorithms is presented for the computation of the optimal thresholds. The algorithm consists of three major components: a population space, a belief space, and a communication protocol that describes how knowledge is exchanged between the first two components. The designs and implementations of the three components are given in detail. The experimental results show that the segmentation method proposed in this paper can obtain the near optimal threshold for image segmentation.
Image segmentation is to partition an image into meaningful regions. An image segmentation approach based on chaotic
ant colony algorithm is presented in this paper. The approach performs the image segmentation by selecting the optimal
threshold values, where the multi-threshold values are used. First of all, an entropy function corresponding to an image
is defined. The optimal threshold values are obtained by making the entropy function reach the maximal value.
Secondly, an approach based on ant colony algorithm is presented for the computation of the optimal thresholds. In
order to improve the computation performance of ant colony algorithms, for example, to avoid the algorithm search
being trapped in local optimum, we use chaotic approach to find a better solution whenever all the ants have finished the
operations. The chaotic approach searching the space around the ant which is the best so far. Besides, the initial
solutions are generated by chaotic approach, this improves the quality of initial ants. The experimental results show that
the approach proposed in this paper can get the near optimal threshold.
In medical image processing, the image degradation often occurs. The image restoration is to recover the original image
from its noisy and blurred version. A restoration approach using cultural algorithms for medical images is presented in
this paper. First of all, the representation of image degradation model is built. Secondly, an image is encoded as an
individual; the fitness of an individual is defined. An algorithm based on the principle of cultural algorithms is presented
for obtaining the ideal images from the blurred image. The algorithm consists of the population space, the belief space,
and the communication protocol that describes the exchange mode of knowledge between the population space and
belief space. A few type of knowledge, such as the situational knowledge and the normative knowledge etc., are used.
The images with better quality are obtained by the evolution of populations. The experimental results show that the
image restoration approach proposed in this paper can obtain the good approximations of the original image.
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