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Nanosheet device architectures, such as nanosheet (NS), forksheet (FS), and complementary FET (CFET), are promising to replace FinFET (FF) and enable further CMOS scaling in 3nm CMOS technology node and beyond thanks to wider effective transistor width per footprint.
Key differences in NS integration from FF integration exist in Si/SiGe multilayer active, inner spacer, channel release, and replacement metal gate (RMG) patterning. Si/SiGe multilayer active requires an etch process that does not damage SiGe, and low temperature fill & recess to reduce Ge diffusion. Inner spacer is a common important module for NS, FS, and CFET to reduce parasitic capacitance, where precise lateral etch control and high etch selectivity are necessary in Si or SiGe cavity selective etch and inner dielectric isotropic etch. Channel release is an essential process step to enable nanosheet architectures, which needs high selective SiGe or Si etch. A post clean without residue, surface roughness, and NS stiction is required. In RMG patterning, work function metal removal in NS-NS vertical space without N-P space increase is important, which is enabled by introducing sacrificial pattering cap layer and faster etch rate in WFM or sacrificial layer seams.
FS improves scalability of N-P patterning in SD epi and RMG patterning by reducing hard mask (HM) patterning aspect ratio on dielectric wall. However, high HM etch selectivity to dielectric wall and HM edge placement error on dielectric wall are crucial. In addition, a tall & narrow-space active patterning is necessary in FS to enable dielectric wall and RMG patterning on dielectric wall.
CFET enables ultimate CMOS scaling by N-P stacking architecture. However, the N-P stacking architecture creates process challenges. Monolithic CFET integration enables self-aligned active/gate/contact patterning. But it needs high aspect ratio patterning and vertical patterning for SD & contact, and RMG. Sequential CFET simplifies SD, RMG and contact integration by separating the process flow into top and bottom device [5]. But it needs wafer transfer without bonding defects, precise litho alignment between top and bottom processes and top-bottom gate connection. High aspect ratio via integration is a common challenge in monolithic and sequential CFET.
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