A 200 Million Operations Per Second (MOPS) Systolic Processor

J. Blackmer; G. Frank; P. Kuekes

doi:10.1117/12.932506

30 July 1982 A 200 Million Operations Per Second (MOPS) Systolic Processor

J. Blackmer, G. Frank, P. Kuekes

Proceedings Volume 0298, Real-Time Signal Processing IV; (1982) https://doi.org/10.1117/12.932506
Event: 25th Annual Technical Symposium, 1981, San Diego, United States

Abstract

In building a proof of concept model of a systolic processor, several design issues are resolved. Flexibility is achieved through a hierarchy of software which resides on a host computer and through extensive interface and control hardware. Buffer memories with pro-grammable address generators are provided in the interface. The control system is general enough to support command chaining and loops. Each cell of the systolic array is equipped with its own memory which allows a single cell design to perform a number of algorithms. As a result of designing for flexibility, the system can accommodate a wide variety of algorithms, data representations, and problem dimensions. A useful system computation rate of 200 million operations per second (MOPS) is achieved with a peak rate of 350 MOPS.

Citation Download Citation

J. Blackmer, G. Frank, and P. Kuekes "A 200 Million Operations Per Second (MOPS) Systolic Processor", Proc. SPIE 0298, Real-Time Signal Processing IV, (30 July 1982); https://doi.org/10.1117/12.932506

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