A 50Mbit/Sec. CMOS Video Linestore System

Yeun C. Jeung

doi:10.1117/12.968974

25 October 1988 A 50Mbit/Sec. CMOS Video Linestore System

Yeun C. Jeung

Proceedings Volume 1001, Visual Communications and Image Processing '88: Third in a Series; (1988) https://doi.org/10.1117/12.968974
Event: Visual Communications and Image Processing III, 1988, Cambridge, MA, United States

Abstract

This paper reports the architecture, design and test results of a CMOS single chip programmable video linestore system which has 16-bit data words with 1024 bit depth. The delay is fully programmable from 9 to 1033 samples by a 10 bit binary control word. The large 16 bit data word width makes the chip useful for a wide variety of digital video signal processing applications such as DPCM coding, High-Definition TV, and Video scramblers/descramblers etc. For those applications, the conventional large fixed-length shift register or static RAM scheme is not very popular because of its lack of versatility, high power consumption, and required support circuitry. The very high throughput of 50Mbit/sec is made possible by a highly parallel, pipelined dynamic memory architecture implemented in a 2-um N-well CMOS technology. The basic cell of the programmable video linestore chip is an four transistor dynamic RAM element. This cell comprises the majority of the chip's real estate, consumes no static power, and gives good noise immunity to the simply designed sense amplifier. The chip design was done using Bellcore's version of the MULGA virtual grid symbolic layout system. The chip contains approximately 90,000 transistors in an area of 6.5 x 7.5 square mm and the I/Os are TTL compatible. The chip is packaged in a 68-pin leadless ceramic chip carrier package.

Citation Download Citation

Yeun C. Jeung "A 50Mbit/Sec. CMOS Video Linestore System", Proc. SPIE 1001, Visual Communications and Image Processing '88: Third in a Series, (25 October 1988); https://doi.org/10.1117/12.968974

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