CONFERENCE PROCEEDINGS
Advanced Search
Home > Proceedings > Volume 10145 > Article
Presentation
25 May 2017 SEM review color imaging detection of gate to source/drain short in 14nm finFET device (Conference Presentation)
Kwame Owusu-Boahen, JaeHun Park, HyeJung Lee
Author Affiliations +
Proceedings Volume 10145, Metrology, Inspection, and Process Control for Microlithography XXXI; 101451T (2017) https://doi.org/10.1117/12.2253723
Event: SPIE Advanced Lithography, 2017, San Jose, California, United States
Abstract
The introduction of finFET has contributed tremendously in making scaling beyond 20nm a reality. However, the complexity of these 3D high performance transistors generate inherent new defects that are difficult to detect and this heightens concerns over device quality and reliability at future technology nodes. New methods and approaches are thus needed to effectively detect and monitor this new class of defects. Color imaging in Scanning Electron Microscopy (SEM) is not a new phenomenon. However, its use in inline SEM based defect review in the semiconductor industry is relatively new. In this work SEM color imaging is used to enhance SEM review redetection of a buried defect, Gate to Source/Drain short in 14nm finFET device. Defect sites on the wafer are flagged as defect events by Bright Field (BF) defect inspection tools. The review tool uses SEM optics to redetect the defect event using a combination of very high electron landing energies in excess of 5 keV and high beam current of about 3,000 pA to confirm the existence of the defect. The defect signal is further processed through a color coder by the SEM review equipment to create a “false” color image to enhance defect redetection and help to accurately classify defect.
Conference Presentation
© (2017) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Citation Download Citation
Kwame Owusu-Boahen, JaeHun Park, and HyeJung Lee "SEM review color imaging detection of gate to source/drain short in 14nm finFET device (Conference Presentation)", Proc. SPIE 10145, Metrology, Inspection, and Process Control for Microlithography XXXI, 101451T (25 May 2017); https://doi.org/10.1117/12.2253723
ACCESS THE FULL ARTICLE
ORGANIZATIONAL
Sign in with credentials provided by your organization.
INSTITUTIONAL
Select your institution to access the SPIE Digital Library.
SELECT YOUR INSTITUTION
PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.
PERSONAL SIGN IN
No SPIE Account? Create one
PURCHASE THIS CONTENT
SUBSCRIBE TO DIGITAL LIBRARY
50 downloads per 1-year subscription
Members: $195
Non-members: $335 ADD TO CART
25 downloads per 1 - year subscription
Members: $145
Non-members: $250 ADD TO CART
PURCHASE SINGLE ARTICLE
Includes PDF, HTML & Video, when available
Members: $17.00
Non-members: $21.00 ADD TO CART
PROCEEDINGS
 PRESENTATION
WATCH
PRESENTATION SAVE TO MY LIBRARY
GET CITATION
Advertisement
Advertisement
KEYWORDS
Scanning electron microscopy
Color imaging
Signal processing
Image processing
Semiconductors
Defect inspection
Semiconducting wafers
RELATED CONTENT
Subscribe to Digital Library
Receive Erratum Email Alert
Back to Top