3.1

Panchromatic detector

The next figure shows the basic architecture of the panchromatic detector.

The image section has 6000(H) x N(V) active pixels each 13 μm square and is clocked continuously to give a time-delay-and-integrate (TDI) function. The transfer of charge along the CCD is made synchronous with the velocity of the scan image. The integration time is N_i times longer than a single-detector integration time, where N_i is the number of TDI stages. Since the noise is proportional to N_i ^1/2, the SNR improvement over a single detector is also N_i ^1/2. Within the image section are 4 separately connected electrode groups to enable the TDI length N_i to be varied.

Below the image section is a register that is split into 10 sections, each with a separate output circuit. The 5 sections on the right hand side transfer to the right and the 5 sections on the left hand side transfer to the left. Between the image section and the register are additional buffer rows with some of the buffer path slanted to make room for the output circuits. The last parallel transfer electrode is a transfer gate. At the top of the image section is a connection for the “antiblooming” drains that are necessary for the method of TDI length selection. The chip is left-right symmetrical about the central line.

The electrodes of the image section are of the four-phase type (designated IΦ₁ to IΦ₄). The clock sequences foreseen to be used for device operation causes charges to be stored under a pair of adjacent electrodes.

The method for varying the number of TDI stages is as follows. Down each inter columns isolation structure is a drain of type normally used for anti-blooming purposes. Four groups of IΦ₃ electrodes are separately connected and designated A, B, C and D. These electrodes are normally clocked with IΦ₃ but any group can be held at a suitably low constant voltage to block charge transfer down the array. Signal charge accumulates under the electrodes of the preceding pixel and any charge in excess of the full well capacity is lost in the drain. The TDI length is then the number of pixel rows in the normally clocked image section below the selected group. Any selected group can always revert to normal clocking and others be selected to change TDI length, but time may have to elapse for the charge accumulated in electrodes of the pixel above the first selected group to be blocked out before correct operation reestablished.

The full-well capacity is set by the processing used to fabricate the device, specifically the channel doping and the anti-blooming “barrier height”, i.e. the well depth at which charge spills to drain. Some adjustment of the capacity can be possible by adjustment of the drain voltage. The target value is a minimum of 130 k electrons.

Each electrode in the image section has capacitance to substrate and also, as a result of the method of vertical connections, to most of the other phases. The total load per phase is that to substrate plus the various inter-phase components. The values for the clocks IΦ_i are approximately 3 to 4 nF. These values have a very strong impact on the detector performances and on the detection electronics design as the effect of the resistance of the metal and polysilicon connecting tracks is to slow the rise and fall times of the drive pulses applied by the detection electronics. The worst case slowing is at the device center in the last row before the transfer gate. The RC time constant is however relatively short, estimated at 0,15 μs, with the result that very fast drive pulse edges the times for the internal waveforms to change between 10% and 90% levels will be no more than 0,5 μs.

The output circuit has a charge conversion factor of 2 μV/electron capable of sufficiently fast settling with 10 pF external load to give an output waveform with essentially flat reset and signal sampling intervals each of 20 ns (the video rate for the Pléiades is 6,5 Mpixels per second for each panchromatic detector ouput).

The dissipation value expected for each PAN device is 1,5 W total, with about 1 W on-chip.

3.2

Multispectral detector

For the multispectral detector, the photo-sensing element of the pixel is a photodiode. The detector consists of 4 lines of photodiodes, the spacing between the centers of each line and the next being 936 μm. Each line of pixels has 1,500 photo-elements on a 52 μm pitch and the size of each photo-element is 52 μm square. Signal charge generated in the photodiode is initially collected under an adjacent CCD electrode. Transfer of charge from the storage gate to the read-out register is performed by a transfer gate. An antiblooming structure is implemented in the storage gate. The register is a 2 phases structure, with a pitch of 26 μm. Each photo-element charges are stored under two pairs of adjacent electrodes ΦL₁-ΦL₂. Thus the readout register is operated at twice the required pixel frequency (frequency of the ΦL₁-ΦL₂ clocks is 7,4 MHz) and the output signal is recovered after summing in the detector output stage.

The antiblooming function can be adjusted separately for each pixel line. Each line is driven by 2 sets of specific electrodes ΦL₁-ΦL₂, which allow to deselect any of the 4 lines and reduce the power consumption of the chip.

Each pixel line has its own output, which lead to 4 output for the complete chip. The video rate is 3,7 Mpixels per second for each multispectral detector output.

The full-well capacity is far larger than the 130 k electrons minimum saturation requirement.

The values for the clocks ΦL_i are approximately 500 pF. This value is smaller that for the panchromatic detector as up to 8 pairs of ΦL₁-ΦL₂ can be driven on the XS detector.

The dissipation values expected for each XS device is about 2,5 W total, with about 1,2 W on-chip.

The standard detector package consists of a co-fired Aluminum Nitride (AlN) ceramic body with dual in line pins on the underside. The window is in BaK50 with an antireflection coating on both sides.

The spectral selection is made by optical filters placed very close in front of the detectors. XS strip lines filters (Fig. 9) are space-qualified multi-layer coating deposited on glass substrates. Each filter is composed of high-pass filter and low-pass filter. An absorbing material deposited between the XS filters isolates each band from the others to avoid inter-band stray-light.

Fig. 1.

Focal plane assembly

Fig. 2.

Focal plane mechanical structure with detectors

Fig. 3.

Detector mechanical frame with electrical link

Fig. 4.

Focal plane mirrors

Fig. 5.

Architecture of the panchromatic detector

Fig. 6.

TDI length selection

Fig. 7.

Simulated output waveform

Fig. 8.

Multispectral detector architecture

Fig. 9.

XS filter design

Fig. 10.

Organization of a MVP

Fig. 11.

Technological implementation

Fig. 12.

CLBNG functional diagram

Fig. 13.

Phase driving principle

Fig. 14.

HVIDEONG Hybrid

Fig. 15.

ICARE Hybrid

Fig. 16.

MVP mechanical package

Fig. 17.

View of the complete detection electronics

Fig. 18.

View of the Pléiades SEDHI (including the focal plane and the radiators)

4.1

Technological implementation

Future high resolution instruments will require rather large quantities of few basic functions such as video processing chains, CCD phase drivers or LNTHD. For example, quantities are respectively estimated to 70, 220 and 30, in the case of one Pléiades camera. Consequently, feasibility of these future instruments will depend strongly on the availability of those basic functions with good power and size budgets. Unfortunately, standard component from manufacturers have scarcely the right characteristics, in term of functionality, performances or capability to withstand space environment. For video processing, CCD phase driving and digitally programmable delay no satisfactory standard component has been found. For this reason, CNES and Alcatel Space have chosen to develop 3 analogue/mixed ASICs corresponding to these 3 functions.

On the basis of these ASICs, two types of hybrids have also been developed : a video processing hybrid, and a CCD phase driver hybrid. These technological basic functions, ASIC or hybrids, are compatible with most detection electronic architectures, as described above. In that prospect, they can be considered as standard basic functions. Due to their low power and size budgets, these basic functions fulfil the requirements of limiting the mass, volume and power consumption of the complete subsystem which is one of the main goals of the SEDHI concept.

Technological implementation of next generation detection electronics is summarized on the next figure.

4.2

Description of the video modules

Each MVP is constituted of 2 modules:

These two modules are embedded in a mechanical frame, and connected with a rigid printed circuit board. The connection between the CCD and the MVP is performed with a flexible printed circuit which will be the electrical interface between the focal plane and the detection electronics.

The possibility of adjusting the cable length authorizes to have a large number of CCDs in order to constitute very large focal planes.

The main performances tested on the MVP modules have been described in reference 2.

5.1

Mechanical concept

The mechanical and thermal architecture is split in three distinguish parts corresponding to separate hardware modules: the focal plane, the electronics modules, the focal plane radiator.

Each element is supported independently by the telescope’s structure with the help of mechanical frames and supporting blades.

Several configurations of focal plane may be considered depending on the application, and for Pléiades one will consider optically butted linear detectors.

The focal plane structure holds the detectors and insures the thermal conductivity between the detectors and the external thermal drain. The thermal flux dissipated by the detectors are dissipated in space through the focal plane space radiator.

Each electronics PCB is mounted in an individual mechanical frame to constitute a MVP. These modules are stacked together and screwed on a specific mechanical frame. The following figure shows the MVP mechanical package.

This architecture authorizes a very flexible mechanical architecture, which can be easily adapted to a wide range of focal plane requirements (number of detectors, length of the focal plane..), with a minimization of engineering efforts.

5.2

Thermal concept

The thermal concept must handle the heat generated by the detectors in the focal plane and by the MVPs.

The focal plane radiator size depends directly on the detectors power dissipation which is directly related to their operating frequency. The radiator sketched on figure showing the complete SEDHI must handle a detector power dissipation close to 20 W. The focal plane structure is thermally coupled to the radiator by cooper wires and/or heat pipes. The radiator is fixed on the telescope structure by insulation blades.

The MVP are thermally regulated by the radiated surface opposite to the MVP mechanical interface. The available surface is sufficient to limit the temperature of each module to a temperature compatible with the radiometric requirements. No thermal drain is required as the heat is conducted through the mechanical structure of each MVP.

5.3

SEDHI for Pléiades

The concept of SEDHI can be advantageously used for instrument with a high number of detectors like Pléiades.

The full detection electronics consist in 5 panchromatic MVPs, 3 multispectral MVPs, 3 panchromatic MSP (embedded in a single mechanical module) and 1 multispectral MSP. The Pléiades instrument electronics include the MVP functions, the MSP (Module de Servitude de Proximité) and the MSI (Module de Servitude Instrument) dedicated to command / control. The PAN detection electronics is divided in 3 blocks:

The XS detection electronics is constituted of 3 MVPs (one of them associated to a single XS detector) and 1 MSP.

Each MVP PAN may provide up to 20 clocks to the PAN detector (24 for the MVP XS). Each clock is transmitted on a line which is specifically adapted, taking into account the connector and CCD input impedances.

The video interfaces between the detector outputs and the MVP are pseudo-differential, which is the best choice for Pléiades due to the electrical and thermal constraints.

All the sequencing functions of the MVP are integrated in a digital ASIC called SAPHO, which is common to PAN and XS and which can be easily configured for each of the sequencing modes. This ASIC receives the master clock from the MSP, and generates all the clocks required for the detectors, video processing and digital outputs synchronization. It also receives from the MSP the configuration data for mode selection and initialization of all parameters.

The video data after digitization by the Analog to Digital Converters in the HVIDEONG hybrids are transmitted to the Pléiades Compression Unit in the satellite. The data formatting and the transmission via High Speed Data link (LNTHD) is performed with a digital ASIC called MURANO. This ASIC also generates test pattern and it performs the multiplexing of the 12 bits of each of the video channels (5 for PAN, each MVP PAN having 2 LNTHD, and 4 for XS, each MVP XS having 2 LNTHD). Each LNTHD is redounded.

Due to the very high level of integration, a large number of critical signals are transmitted inside each MVP: high speed clocks, high speed digital links, phase trimming clocks, video signals, high level CCD clocks. In order to guarantee the integrity of each of these signals, and to limit the possible effects of close neighboring of critical signals, many precautions have been taken. They include an important segregation of functions of different type, the use of adapted links (differential or pseudodifferential), the optimization of parasitic capacitance and the use of signal integrity and simulation tools to analyze and optimize the electrical diagram.

The main budgets associated to the Pléiades detection electronics are summarized on next table.