Methodology For Reduction Of Sampling On The Visual Inspection Of Developed And Etched Wafers

Jamie S. VanDeVen; Fred Khorasani

doi:10.1117/12.953124

19 July 1989 Methodology For Reduction Of Sampling On The Visual Inspection Of Developed And Etched Wafers

Jamie S. VanDeVen, Fred Khorasani

Proceedings Volume 1087, Integrated Circuit Metrology, Inspection, and Process Control III; (1989) https://doi.org/10.1117/12.953124
Event: 1989 Santa Clara Symposium on Microlithography, 1989, San Jose, CA, United States

Abstract

There is a lot of inspection in the manufacturing of semiconductor devices. Generally, the more important a manufacturing step, the higher is the level of inspection. In some cases 100% of the wafers are inspected after certain steps. Inspection is a non-value added and expensive activity. It requires an army of "inspectors," often times expensive equipment and becomes a "bottle neck" when the level of inspection is high. Although inspection helps identify quality problems, it hurts productivity. The new management, quality and productivity philosophies recommend against over inspection. [Point #3 in Dr. Deming's 14 Points for Management (1)] 100% inspection is quite unnecessary . Often the nature of a process allows us to reduce inspection drastically and still maintain a high level of confidence in quality. In section 2, we discuss such situations and show that some elementary probability theory allows us to determine sample sizes and measure the chances of catching a bad "lot" and accepting a good lot. In section 3, we provide an example and application of the theory, and make a few comments on money and time saved because of this work. Finally, in section 4, we draw some conclusions about the new quality and productivity philosophies and how applied statisticians and engineers should study every situation individually and avoid blindly using methods and tables given in books.

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Jamie S. VanDeVen and Fred Khorasani "Methodology For Reduction Of Sampling On The Visual Inspection Of Developed And Etched Wafers", Proc. SPIE 1087, Integrated Circuit Metrology, Inspection, and Process Control III, (19 July 1989); https://doi.org/10.1117/12.953124

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KEYWORDS

Inspection

Semiconducting wafers

Process control

Manufacturing

Integrated circuits

Metrology

Optical inspection

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