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Reducing process development time and speeding up time to market are perennial challenges in the microelectronics industry. The development of etch models that permit optimizations across the wafer would enable manufacturers to optimize process design flows and predict process defects before a single wafer is run. The challenges of across-wafer uniformity optimizations include the large variety of features across the wafer, etch variations that occur at multiple scales within the plasma chamber, feature metrology, and computationally expensive model development. Compounding these challenges are trade-offs between data quality and time/cost-effectiveness, the wide variety of measurement information provided by different tools, and the sparsity and inconsistency of human-collected data. We address these challenges with a feature and wafer level modeling approach. First, experiments are conducted for a variety of etch conditions (e.g., pressure, gas composition, flow rate, temperature, power, and bias). Second, a feature level model is calibrated at multiple sites across the wafer based on OCD and/or cross-sectional SEM measurements. Finally, the calibrated model is used to predict an optimal set of process conditions to preserve uniformity across the wafer and to meet recipe targets. We demonstrate the methodology using SandBox Studio™ AI for a FinFET application. Specifically, we show the rapid and automated calibration of feature level models using experimental measurements of the 3D feature etch at a variety of process conditions. Automated image segmentation of X-SEM data is also performed here for single case using Weave® to demonstrate how such data can be acquired quickly in a development environment. We then demonstrate the effectiveness of the reduced-order model to predict optimal recipe conditions to improve overall recipe performance. We show how, with this hybrid-metrology computational approach, a process window that yields 89.2% of the wafer can be captured.
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