Paper
28 March 2023 Design and optimization of asynchronous FIFO based on Verilog HDL
Zhuoqun Cheng
Author Affiliations +
Proceedings Volume 12597, Second International Conference on Statistics, Applied Mathematics, and Computing Science (CSAMCS 2022); 125972O (2023) https://doi.org/10.1117/12.2672684
Event: Second International Conference on Statistics, Applied Mathematics, and Computing Science (CSAMCS 2022), 2022, Nanjing, China
Abstract
SoC system is a new chip design scheme, which can integrate a large number of functions in the same chip, so it has high requirements for asynchronous data transmission between different modules. Asynchronous FIFO is an efficient and reliable data transmission mode, which is often used as a data matcher in SoC system. This paper, through the modular design, layer by layer construction method, designs an asynchronous FIFO, and for the common problems to optimize, makes its performance more reliable. And according to the simulation results, it can be judged that this design can effectively and reliably carry out asynchronous data transmission.
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Zhuoqun Cheng "Design and optimization of asynchronous FIFO based on Verilog HDL", Proc. SPIE 12597, Second International Conference on Statistics, Applied Mathematics, and Computing Science (CSAMCS 2022), 125972O (28 March 2023); https://doi.org/10.1117/12.2672684
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KEYWORDS
Design and modelling

Clocks

Data transmission

Data modeling

Binary data

Integrated circuits

Operating systems

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