Verilog implementation of configurable UART module

Zihang Du; Yang Liu; Chaoqun Qiu; Xinmeng Zhang

doi:10.1117/12.2672692

28 March 2023 Verilog implementation of configurable UART module

Zihang Du, Yang Liu, Chaoqun Qiu, Xinmeng Zhang

Proceedings Volume 12597, Second International Conference on Statistics, Applied Mathematics, and Computing Science (CSAMCS 2022); 125972X (2023) https://doi.org/10.1117/12.2672692
Event: Second International Conference on Statistics, Applied Mathematics, and Computing Science (CSAMCS 2022), 2022, Nanjing, China

Abstract

Universal Asynchronous Receiver Transmitter (UART) is widely used in the communication between main devices and peripheral devices with high reliability and simplicity. It can support serial data transmission by a single Tx line and Rx line with prescribed data length and baud rate. This paper proposes a configurable design of UART module based on Verilog HDL. This design features compatibility with multiple UART regulations. The information of configuration is stored in a register using serial transmission and read by other modules. The baud rate, data length, and validation of the verification bit are configurable to fit various UART standards. The functions and simulation results are explained, and the simulation implemented on Modelsim supports the proposal.

Citation Download Citation

Zihang Du, Yang Liu, Chaoqun Qiu, and Xinmeng Zhang "Verilog implementation of configurable UART module", Proc. SPIE 12597, Second International Conference on Statistics, Applied Mathematics, and Computing Science (CSAMCS 2022), 125972X (28 March 2023); https://doi.org/10.1117/12.2672692

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