Mask and reticle acceptance in an ASIC wafer fab

Steven C. Weirauch

doi:10.1117/12.3011938

12 October 2023 Mask and reticle acceptance in an ASIC wafer fab

Steven C. Weirauch

Proceedings Volume 12812, Bay Area Chrome Users Society Symposium 1988; 1281204 (2023) https://doi.org/10.1117/12.3011938
Event: 8th Annual BACUS Symposium, 1988, Sunnyvale, CA, United States

Abstract

Application Specific Integrated Circuit (ASIC) wafer fabrication requires short cycle times and manufacturing flexibility; key elements for success in the ASIC market. The speed with which a new design is translated into working devices depends on many factors. One critical factor is mask and reticle inspection and acceptance. An ASIC environment has numerous processes and a constant stream of new devices creating problems in: inspection, pelliclization, storage and tracking. At VLSI Technology, over 100 plates are received each week from several mask suppliers. Our Incoming Photomask QC group is responsible for the inspection, pelliclization, storage and tracking of these plates. It is very easy for defective plates to be shipped, inspections to be missed or for plates to be incorrectly logged and misfiled. Organization, well-defined procedures, proper training and good working relationships with mask suppliers are imperative to insure all plates meet specifications and are released on time. Procedures and techniques used to accomplish this are presented.

Citation Download Citation

Steven C. Weirauch "Mask and reticle acceptance in an ASIC wafer fab", Proc. SPIE 12812, Bay Area Chrome Users Society Symposium 1988, 1281204 (12 October 2023); https://doi.org/10.1117/12.3011938

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