Design of an analog VLSI chip for a neural network target tracker

Chiewcharn Narathong; Rafael M. Inigo

doi:10.1117/12.45411

1 June 1991 Design of an analog VLSI chip for a neural network target tracker

Chiewcharn Narathong, Rafael M. Inigo

Proceedings Volume 1452, Image Processing Algorithms and Techniques II; (1991) https://doi.org/10.1117/12.45411
Event: Electronic Imaging '91, 1991, San Jose, CA, United States

Abstract

Real—time visual tracking is a difficult problem requiring high speed processing. Neural networks have shown great potential for solving the problem. We have recently reported a two—layer Hopfield—Tank (HT) network implementation of a fast tracking algorithm capable of estimating displacements from a sequence of images [1]. In this paper we have taken a step further. That is, we have designed a custom analog VLSI chip capable of computing target motion parameters. To date, a number of researchers have constructed small—scale networks with less than 100 neurons as well as large—scale networks with up to 1000 neurons, both with feedback and feedforward architectures [2,3]. Small networks have been limited in size by VLSI real— estate considerations as well as its internal wiring. Large network have been constructed using "building block" paradigms. These building blocks are known as synapse and neuron. A synapse chip contains many synapse cells. Similarly, a neuron chip contains only neuron cells. A neuroprocessor is formed by connecting many of these chips together. Signals are routed off—chip. Hence, speed is slower than a single chip design. However, a large network with different architectures can be implemented with these building blocks. Our design is based on a single chip design. The single chip design was chosen in order to satisfy the high speed required for our application. This paper first briefly presents the overall architecture of the network. Individual cell design then follows together with its SPICE simulations.

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Chiewcharn Narathong and Rafael M. Inigo "Design of an analog VLSI chip for a neural network target tracker", Proc. SPIE 1452, Image Processing Algorithms and Techniques II, (1 June 1991); https://doi.org/10.1117/12.45411

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KEYWORDS

Neurons

Network architectures

Transistors

Very large scale integration

Amplifiers

Analog electronics

Neural networks

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