Design of a Gaussian elimination architecture for the DOC II processor

Miles Murdocca

doi:10.1117/12.2321740

1 December 1991 Design of a Gaussian elimination architecture for the DOC II processor

Miles Murdocca

Proceedings Volume 1563, Optical Enhancements to Computing Technology; (1991) https://doi.org/10.1117/12.2321740
Event: San Diego, '91, 1991, San Diego, CA, United States

Abstract

The OptiComp DOC II processor serves as the basis for the design of a hybrid optical/electronic architecture that solves systems of linear equations using Gaussian elimination. The architecture consists of a cascade of acoustooptic modulator based programmable logic arrays (PLAs) operating at a rate of 100MHz. Arithmetic operations are performed using 16-bit fixed point arithmetic, and include subtraction, multiplication and division. The design goal is to solve a system of linear equations in 10 unknowns in under 20 µs, for a target application of null steering for phased array radar. The design goal is achieved with reasonable complexity.

Citation Download Citation

Miles Murdocca "Design of a Gaussian elimination architecture for the DOC II processor", Proc. SPIE 1563, Optical Enhancements to Computing Technology, (1 December 1991); https://doi.org/10.1117/12.2321740

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