Efficient bit-level systolic arrays for QMF banks

Chia-Wen Lin; Yung-Chang Chen; Chin-Liang Wang

doi:10.1117/12.131374

1 November 1992 Efficient bit-level systolic arrays for QMF banks

Chia-Wen Lin, Yung-Chang Chen, Chin-Liang Wang

Proceedings Volume 1818, Visual Communications and Image Processing '92; (1992) https://doi.org/10.1117/12.131374
Event: Applications in Optical Science and Engineering, 1992, Boston, MA, United States

Abstract

In this paper, various systolic arrays are proposed for the application to quadrature mirror filter (QMF) banks. A word-level systolic array is firstly presented to realize QMF banks. It is subsequently refined to bit-level array with bit-parallel arithmetic via the well-known two-level pipelining techniques and is then converted to bit-serial form by using the bit-serial inner product array proposed by Wang et al.. By applying the polyphase representation as well as fully utilizing the special relations among QMFs', aside from the memory cost, the whole filter bank can be constructed by using only about one half of the hardware expense of a prototype filter. In comparison with the direct realization using polyphase representation, the number of the systolic multiplier-accumulators (SMAs) required for our architecture is halved. Thus, both the chip area and transistor-count are reduced. As a result, with today's commercial CMOS technology, the whole filter bank can be implemented within a single-chip for various video applications.

Citation Download Citation

Chia-Wen Lin, Yung-Chang Chen, and Chin-Liang Wang "Efficient bit-level systolic arrays for QMF banks", Proc. SPIE 1818, Visual Communications and Image Processing '92, (1 November 1992); https://doi.org/10.1117/12.131374

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