Optical and electronic error correction schemes for highly parallel access memories

Mark Allen Neifeld; Jerry D. Hayes

doi:10.1117/12.163604

9 November 1993 Optical and electronic error correction schemes for highly parallel access memories

Mark Allen Neifeld, Jerry D. Hayes

Proceedings Volume 2026, Photonics for Processors, Neural Networks, and Memories; (1993) https://doi.org/10.1117/12.163604
Event: SPIE's 1993 International Symposium on Optics, Imaging, and Instrumentation, 1993, San Diego, CA, United States

Abstract

We have fabricated and tested an optically addressed, parallel electronic Reed-Solomon decoder for use with parallel access optical memories. A comparison with various serial implementations has demonstrated that for many instances of code block size and error correction capability, the parallel approach is superior from the perspectives of VLSI layout area and decoding latency. The demonstrated Reed-Solomon parallel pipeline decoder operates on 60 bit input words and has been demonstrated at a clock rate of 5 MHz yielding a demonstrated data rate of 300 Mbps.

Citation Download Citation

Mark Allen Neifeld and Jerry D. Hayes "Optical and electronic error correction schemes for highly parallel access memories", Proc. SPIE 2026, Photonics for Processors, Neural Networks, and Memories, (9 November 1993); https://doi.org/10.1117/12.163604

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