Test chip fabrication of 3D optically coupled common memory for parallel processing system

Mitsumasa Koyanagi; Koji Miyake; Shin Yokoyama; Masataka Hirose; Tadashi Ae; Yasuhiro Horiike

doi:10.1117/12.206304

5 April 1995 Test chip fabrication of 3D optically coupled common memory for parallel processing system

Mitsumasa Koyanagi, Koji Miyake, Shin Yokoyama, Masataka Hirose, Tadashi Ae, Yasuhiro Horiike

Proceedings Volume 2400, Optoelectronic Interconnects III; (1995) https://doi.org/10.1117/12.206304
Event: Photonics West '95, 1995, San Jose, CA, United States

Abstract

We have proposed a new three-dimensional optically coupled common memory (3D-OCC memory) to solve the problem of bus bottle neck in the multi-processor system with the shared memories. Three-dimensional-OCC memory consists of several memory layers vertically stacked and a block of data is simultaneously transferred among these memories using vertically optical interconnection. Three-dimensional-OCC memory acts as the real shared memory. Three-dimensional-OCC memory test chip has been fabricated using 2 micrometers CMOS technology. LEDs are integrated on the silicon test chip by using a newly developed micro-bonding technology. We observed the uniform photon emission from these LEDs. In addition, the basic operation of 3D-OCC memory for optical writing/electrical reading was confirmed using this test chip.

Citation Download Citation

Mitsumasa Koyanagi, Koji Miyake, Shin Yokoyama, Masataka Hirose, Tadashi Ae, and Yasuhiro Horiike "Test chip fabrication of 3D optically coupled common memory for parallel processing system", Proc. SPIE 2400, Optoelectronic Interconnects III, (5 April 1995); https://doi.org/10.1117/12.206304

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