VLSI chip-set for affine-based video compression

Omid Fatemi; Sethuraman Panchanathan

doi:10.1117/12.235421

22 March 1996 VLSI chip-set for affine-based video compression

Omid Fatemi, Sethuraman Panchanathan

Proceedings Volume 2668, Digital Video Compression: Algorithms and Technologies 1996; (1996) https://doi.org/10.1117/12.235421
Event: Electronic Imaging: Science and Technology, 1996, San Jose, CA, United States

Abstract

A crucial operation in image and video processing applications is affine transforms. Typical applications of affine transforms include fractal block coding, camera operation detection, affine motion estimation, etc. Affine transforms involve complex operations and are hence difficult to implement in real-time. In this paper, we present a novel architecture for real-time implementation of affine transforms. First, we derive two fundamental operations from affine transforms and then propose an efficient method of implementing these operations. As an example of the application of ATP (Affine Transform Processor), we propose a high performance video compression algorithm mapped onto the proposed architecture. This algorithm is based on combined affine transform and vector quantization (ATVQ), where the infra-frame and inter-frame redundancy in the video sequence are exploited through piecewise self-similarity on a block-wise basis within a frame and between frames. ATVQ has the advantages of superior coding performance at a significantly reduced computational complexity. ATVQ has been mapped onto the ATP and real-time execution is demonstrated using a VHDL (VHSIC Hardware Description Language) implementation of ATP.

Citation Download Citation

Omid Fatemi and Sethuraman Panchanathan "VLSI chip-set for affine-based video compression", Proc. SPIE 2668, Digital Video Compression: Algorithms and Technologies 1996, (22 March 1996); https://doi.org/10.1117/12.235421

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