Paper
28 July 1997 Application of charge-dispersing layer to reticle fabrication
Kotaro Shirabe, Eiichi Hoshino, Keiji Watanabe
Author Affiliations +
Abstract
The surface imaging (SI) technique to apply to reticle fabrication was investigated. We have proposed an electron- beam (EB) bi-level resist system to fabricate reticles for 1- Gbit DRAMs. The SI technique does not have only an effect to plane the surface of substrate with steps but also good performance to achieve high resolution due to thinner resist as a top layer. It was also found that there was no proximity effect correction to be needed to create the high accuracy patterns on the reticle by using bi-level process. This effect is caused from the reason why Cr and Cr oxide of which mask materials are consisted reflects forwarded electrons strongly. So the resist film in the region near by the surface of opaque film was easily affected by undesirable secondary electrons. For this purpose we made an experiment to set these phenomena in order. Figure 1 and figure 2 shows resist images of contact hole designs on reticles by using bi-level and conventional method respectively. We could find this technique useful to improve quality of corner round because according to properties of line width, the amount of exposed energy was quite different in each case even if every resist was given the same dosage.
© (1997) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Kotaro Shirabe, Eiichi Hoshino, and Keiji Watanabe "Application of charge-dispersing layer to reticle fabrication", Proc. SPIE 3096, Photomask and X-Ray Mask Technology IV, (28 July 1997); https://doi.org/10.1117/12.277270
Advertisement
Advertisement
RIGHTS & PERMISSIONS
Get copyright permission  Get copyright permission on Copyright Marketplace
KEYWORDS
Reticles

Chromium

Electrons

Photoresist processing

Standards development

Electron beam lithography

Fabrication

Back to Top