Manufacturing multilevel metal CMOS with deuterium anneals for improved hot-carrier reliablility

Isik C. Kizilyalli; G. Abeln; Zhi Chen; Gary R. Weber; F. Register; Edward B. Harris; Sundar Chetlur; G. S. Higashi; M. Schofieled; Sidhartha Sen; B. Kotzias; Pradip K. Roy; Joseph W. Lyding; Karl Hess

doi:10.1117/12.323960

4 September 1998 Manufacturing multilevel metal CMOS with deuterium anneals for improved hot-carrier reliablility

Isik C. Kizilyalli, G. Abeln, Zhi Chen, Gary R. Weber, F. Register, Edward B. Harris, Sundar Chetlur, G. S. Higashi, M. Schofieled, Sidhartha Sen, B. Kotzias, Pradip K. Roy, Joseph W. Lyding, Karl Hess

Author Affiliations +

Proceedings Volume 3506, Microelectronic Device Technology II; (1998) https://doi.org/10.1117/12.323960
Event: Microelectronic Manufacturing, 1998, Santa Clara, CA, United States

Abstract

This paper discuses new experimental findings critical for process integration of deuterium post-metal anneals to manufacturing multi-level metal CMOS integrated circuits. Detailed account of the optimization experiments using the deuterium process is given varying temperature (400 - 450 C), time (0.5 - 5 hr), and ambient (10 - 100% D₂). It is shown that the deuterium/hydrogen isotope effect is a general property of MOS wear-out by evaluating many transistor structures from various CMOS technologies. Physical insight into the transistor degradation mechanisms is provided via fundamental STM Si-H(D) desorption experiments and physics based simulations.

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Isik C. Kizilyalli, G. Abeln, Zhi Chen, Gary R. Weber, F. Register, Edward B. Harris, Sundar Chetlur, G. S. Higashi, M. Schofieled, Sidhartha Sen, B. Kotzias, Pradip K. Roy, Joseph W. Lyding, and Karl Hess "Manufacturing multilevel metal CMOS with deuterium anneals for improved hot-carrier reliablility", Proc. SPIE 3506, Microelectronic Device Technology II, (4 September 1998); https://doi.org/10.1117/12.323960

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