Determining and reducing the overhead losses in an ASIC-type environment

Dennis B. Ames

doi:10.1117/12.389085

5 July 2000 Determining and reducing the overhead losses in an ASIC-type environment

Dennis B. Ames

Proceedings Volume 4000, Optical Microlithography XIII; (2000) https://doi.org/10.1117/12.389085
Event: Microlithography 2000, 2000, Santa Clara, CA, United States

Abstract

With the reduce cycle times required to produce customized chips to the end user, the inherent overhead time that is involved with running small lots or even send ahead wafers need to be minimized and optimized to provide reasonable levels of raw throughput. By understanding the process, from the completion of one lot to the start of the next, measurements and actions can be undertaken to outline improvements in the process.

Citation Download Citation

Dennis B. Ames "Determining and reducing the overhead losses in an ASIC-type environment", Proc. SPIE 4000, Optical Microlithography XIII, (5 July 2000); https://doi.org/10.1117/12.389085

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available