Optical area I/O enhanced FPGA with 256 optical channels per chip

Marnik Brunfaut; Jo Depreitere; Wim Meeus; Jan M. Van Campenhout; Hans M. Melchior; Richard Annen; Patrick Zenklusen; Ronny Bockstaele; Luc Vanwassenhove; Jonathan L. Hall; Andreas Neyer; Bjoern Wittmann; Paul L. Heremans; Jan Van Koetsem; Roger King; Hugo Thienpont; Roel G. Baets

doi:10.1117/12.386899

24 May 2000 Optical area I/O enhanced FPGA with 256 optical channels per chip

Marnik Brunfaut, Jo Depreitere, Wim Meeus, Jan M. Van Campenhout, Hans M. Melchior, Richard Annen, Patrick Zenklusen, Ronny Bockstaele, Luc Vanwassenhove, Jonathan L. Hall, Andreas Neyer, Bjoern Wittmann, Paul L. Heremans, Jan Van Koetsem, Roger King, Hugo Thienpont, Roel G. Baets

Author Affiliations +

Proceedings Volume 4089, Optics in Computing 2000; (2000) https://doi.org/10.1117/12.386899
Event: 2000 International Topical Meeting on Optics in Computing (OC2000), 2000, Quebec City, Canada

Abstract

It is our goal to demonstrate the viability of massively parallel optical interconnections between electronic VLSI chips. This is done through the development of the technology necessary for the realization of such interconnections, and the definition of a systems architecture in which these interconnections play a meaningful role. Field-programmable gate arrays (FPGA) have been identified as a class of general-purpose very large scale integration components that could benefit from the massive introduction of state-of-the-art optical inter-chip interconnections at the logic level. In this paper, we present the realization of a small-scale optoelectronic FPGA with 8 X 8 logic cells, containing two optical sources and two receivers per FPGA cell yielding a total of 256 links per chip. These FPGA chips designed to operate with information rates of 80 Mbit/s/link will be used in a three- chip demonstrator system as a test bed for the concepts above. We first identify the reason why we think optical interconnects can provide added value in FPGAs. The next sections briefly discuss the general architecture of our demonstrator system and the realization of the optoelectronic FPGA. We then present first measurement results followed by ongoing work and conclusions.

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Marnik Brunfaut, Jo Depreitere, Wim Meeus, Jan M. Van Campenhout, Hans M. Melchior, Richard Annen, Patrick Zenklusen, Ronny Bockstaele, Luc Vanwassenhove, Jonathan L. Hall, Andreas Neyer, Bjoern Wittmann, Paul L. Heremans, Jan Van Koetsem, Roger King, Hugo Thienpont, and Roel G. Baets "Optical area I/O enhanced FPGA with 256 optical channels per chip", Proc. SPIE 4089, Optics in Computing 2000, (24 May 2000); https://doi.org/10.1117/12.386899

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